Re: [EE]: PCB layout of crystal oscillator for MCU

Hi Sean,

I remove the NFZ and replace it by a ground fill instead.
This probably sounds more logical and matches the recommendations I read on
the webs.

Don't know why I miss this in 1st place.
Thanks.

WH Tan



On Fri, 21 Aug 2026 at 20:31, WH <[email protected]> wrote:

> Hi Sean,
>
> My board stack up are as following:
>
> Top layer: Mostly signal traces, with ground pour to the entire board area.
> 2nd layer: Mostly ground pour, with some signal traces.
> 3rd layer: Ground pour entire area, with VDD (5V) fill zone to cover all
> VDD vias, and a tiny 3.3V fill zone (about 1 - 2 cm square). 2 signal
> traces  (UART Tx and Rx) are running through the ground pour, and one short
> trace of very low speed digital signal is running through the Vdd zone.
> Bottom layer: Ground pour (almost no signal trace, except a couple of
> parts which cannot be placed on top layer)
>
> The reason I want a void zone for VDD underneath the crystal area is to
> avoid feeding high frequency signal into VDD. Do you think this NFZ is
> unnecessary?
>
> Many thanks.
>
> WH Tan
>
>
> On Fri, 21 Aug 2026 at 12:17, Sean Breheny <[email protected]> wrote:
>
>> Overall it looks very good to me. What are the other layers in your
>> stackup? Why do you want to prevent Vdd fill under the crystal?
>>
>> On Thu, Aug 20, 2026 at 11:00 AM WH <[email protected]> wrote:
>>
>> > Hi,
>> >
>> > This is my very first attempt to layout a crystal oscillator for MCU of
>> > TQFP package. Attached screenshot shows the top layer of 4 layers stack
>> up.
>> > The MCU is PIC18F57Q84-I/PT and the crystal is
>> ABM11W-16.0000MHZ-8-B1U-T3.
>> > Link: ABM11W-16.0000MHZ-8-B1U-T3 Abracon LLC | Crystals | DigiKey
>> > <
>> >
>> https://www.digikey.my/en/products/detail/abracon-llc/abm11w-16-0000mhz-8-b1u-t3/7172584
>> > >
>> >
>> > Prior to coming up with the work as shown in attached screenshot, I have
>> > read some application notes and suggestion on the webs but I still have
>> > some doubts.
>> >
>> > 1) The stitching ground vias: should I bring them closer to the crystal?
>> >
>> > 2) The rectangle inside the stitching vias is construction lines I used
>> to
>> > define a no-fill-zone for VDD layer. Should I make it larger to cover
>> the
>> > stitching vias, or smaller to just cover the crystal, or leave it as
>> shown
>> > in the screenshot?
>> >
>> > Appreciate any advice and comments.
>> > Thanks very much.
>> >
>> > --
>> > WH Tan
>> > --
>> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
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>> >
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>>
>
>
> --
> WH Tan
>


-- 
WH Tan