Re: [EE]: PCB layout of crystal oscillator for MCU

Things were much easier twenty years ago with hand etched single layer boards. Admittedly only a 4MHz crystal and bigger parts:



Cheers,
Martin.

On Saturday, 22 August 2026 at 05:59, David VanHorn <[email protected]> wrote:

> Here's what I do, very similar to what you have here.
> 
> I moat the ground on ly1 and ly2 only, and pour ground inside the moat
> on ly1 and ly2.
> Then I route a single track from the crystal area to the ground pin on the
> CPU which is nearest to the crystal pins on the CPU.
> I stitch ly1 and ly2 in the crystal area, but I do NOT stitch them to lower
> layers.
> The idea is that I want whatever currents are flowing to return only and
> directly to the CPU.
> The pin on the CPU where the crystal ground connects is then the only point
> where the crystal ground touches the system ground.
> This prevents any other currents that might be passing through from
> affecting the crystal.
> 
> Ly 3, 4 etc are then clear for use with tracks under the crystal as needed.
> 
> Interesting side note: Check the skin depth in copper for the frequency you
> are running. At lower crystal frequencies a single layer of copper isn't
> thick enough to really isolate the crystal!
> Engineering is the ART of compromise!
> 
> Finally, check your crystal caps.  A crystal that calls out a 22pF load
> capacitance needs significantly larger caps than 22pF!  C = (CL*2)-Cstray.
> Cstray can be estimated at 5 or 6 pF usually. So for 22pF we get (44pf)-5pF
> or 39pF caps.
> On prototypes, I add a series resistor equivalent to 5x the xtal impedance
> in the drive lead to check Barkhausen criteria at high and low temperature
> and high and low operating voltage. If that works, then take the resistor
> out on the final layout.
> If not... :)  Troubleshoot.
> --
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