CPLD and socket board pins mapping
"Simon Wong" <swong-5bdsyQ5pCqFWk0Htik3J/[email protected]>
| Newsgroups | gmane.comp.hardware.microcontrollers.tini |
|---|---|
| Message-ID | <000001c3d646$45b4afb0$3b01000a@baal> |
Hi, I've mounted a CPLD and a regulator onto the 400 socket board. I'm able to load the sample CPLD bitmap from Maxim onto the CPLD. My question is, what are the pin mappings? There's UIO(x) and XIO(y), but I don't know what they do. Are some of them data outputs from the DataPort class? Are some of them address lines from PCE or CE? I can't seem to find documentation on these IO ports. Thanks, Simon Wong _______________________________________________ TINI mailing list TINI-6tN4nzCoH/[email protected] To UNSUBSCRIBE, edit your profile, or see list archives: http://lists.dalsemi.com/mailman/listinfo/tini