Re: GPIO software design question

Thanks Bryan,

I managed to cook a SPI like interface out of the xilinx SPI example and
using the ALE as clock source I'm getting
close to 4Mbit/s. Much less CPU power too - only a single memory write.

And some people were complaining about Dallas support :-). Thanks again.

~Venelin

----- Original Message ----- 
From: "Bryan Armstrong" <bryan.armstrong-6tN4nzCoH/[email protected]>
To: "Venelin Efremov" <[email protected]>
Cc: <swong-5bdsyQ5pCqFWk0Htik3J/[email protected]>; <[email protected]>
Sent: Thursday, January 08, 2004 6:54 AM
Subject: Re: [TINI]GPIO software design question


> Venelin Efremov wrote:
> > On board CPLD won't help you much, since it has no clock input., so you
can
> > not load 8 bits and expect it to send them automatically.
> > Writing in ASM is the key, I managed to get around 1MBps using double
clock
> > speed.
> >
> > ~Venelin
>
> It is possible to use ALE which comes in on IO22 from the TINIs400
> schematic for the CPLD clock.  The ALE signal is 1/4, 1/2, or 1/1 of the
> CPU crystal frequency depending on if you single, double, or quadruple
> it internally on the DS80C400.
>
>
> -- 
> --
> Bryan Armstrong
> bryan.armstrong-6tN4nzCoH/[email protected]
>
>

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