RE: GPIO software design question

Hi,
  Thanks. It is quiet tight for me. I must updgrade my CPLD :(
Thanks

-----Original Message-----
From: Venelin Efremov [mailto:[email protected]] 
Sent: Friday, February 13, 2004 9:57 AM
To: Mujid Abdul-CAM028
Cc: swong-5bdsyQ5pCqFWk0Htik3J/[email protected]; [email protected]; Bryan Armstrong
Subject: Re: [TINI]GPIO software design question


I was using xapp348 as a starting point. You will need to change the ucInterface, since TINI uses non mux address/data bus.

Here is parto of the fitter report output:

Macrocells     Product Terms    Registers      Pins           Function Block
Used           Used             Used           Used           Inputs Used
44 /256 ( 17%) 103 /896  ( 11%) 30 /256 ( 12%) 31 /80  ( 39%) 97 /640 ( 15%)

I shaved quite a bit of the functionality tough. I did not need the clock division, CPOL and CPHA settings.
----- Original Message ----- 
From: "Mujid Abdul-CAM028" <Abdul.Mujid-3WKxDLwmzFNWk0Htik3J/[email protected]>
To: "'Venelin Efremov'" <[email protected]>
Cc: <swong-5bdsyQ5pCqFWk0Htik3J/[email protected]>; <[email protected]>; "Bryan Armstrong" <[email protected]>
Sent: Thursday, February 12, 2004 4:44 PM
Subject: RE: [TINI]GPIO software design question


> Hi,
>   I'm about to try SPI using CPLD(doing some reading).
> Can you provide the link to the example, so that I can jump-start? 
> What is the CPLD utilization in your implementation? Thanks
>
> -----Original Message-----
> From: tini-admin-6tN4nzCoH/[email protected] [mailto:[email protected]] On Behalf 
> Of
Venelin Efremov
> Sent: Tuesday, February 10, 2004 1:33 PM
> To: Bryan Armstrong
> Cc: swong-5bdsyQ5pCqFWk0Htik3J/[email protected]; [email protected]
> Subject: Re: [TINI]GPIO software design question
>
>
> Thanks Bryan,
>
> I managed to cook a SPI like interface out of the xilinx SPI example 
> and
using the ALE as clock source I'm getting close to 4Mbit/s. Much less CPU power too - only a single memory write.
>
> And some people were complaining about Dallas support :-). Thanks 
> again.
>
> ~Venelin
>
> ----- Original Message -----
> From: "Bryan Armstrong" <bryan.armstrong-6tN4nzCoH/[email protected]>
> To: "Venelin Efremov" <[email protected]>
> Cc: <swong-5bdsyQ5pCqFWk0Htik3J/[email protected]>; <[email protected]>
> Sent: Thursday, January 08, 2004 6:54 AM
> Subject: Re: [TINI]GPIO software design question
>
>
> > Venelin Efremov wrote:
> > > On board CPLD won't help you much, since it has no clock input., 
> > > so you
> can
> > > not load 8 bits and expect it to send them automatically. Writing 
> > > in ASM is the key, I managed to get around 1MBps using double
> clock
> > > speed.
> > >
> > > ~Venelin
> >
> > It is possible to use ALE which comes in on IO22 from the TINIs400 
> > schematic for the CPLD clock.  The ALE signal is 1/4, 1/2, or 1/1 of 
> > the CPU crystal frequency depending on if you single, double, or 
> > quadruple it internally on the DS80C400.
> >
> >
> > --
> > --
> > Bryan Armstrong
> > bryan.armstrong-6tN4nzCoH/[email protected]
> >
> >
>
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