Re: MCF5482 Vector#2

Hello Victor,

Victor Remete wrote:
> Subject: [Coldfire] MCF5482 bus cycle termination
>
> There are gaps in the memory map of my processor that are not covered by any of the processor chip selects.  If the code would inadvertently try to access one of these "illegal" addresses, I would like to get a vector#2 exception (called Access Error).  I am not using the MMU and currently the processor just hangs on these accesses.
>
> In the 68000 world this Access Error was called BERR.
>
> Which registers do I use to get this functionality?
>   
How do you have the CACR and ACR regs configured?

When you attempt to access a memory location from the processor (as
opposed to DMA) the address has a number of options.  It is checked
against the RAMBARs, ROMBARs, MBAR.  It is also checked against the
ACRs.  If it doesn't match any of those areas it then defaults to the CACR.

Are you attempting to get a fault from USER or SUPERVISOR mode?  If you
access non-mapped mem from USER mode you can flip the IDSP/DDSP bits and
you'll get a fault.

If you can configure all of the above regs to cover your memory, you can
always enable the MMU with all the TLBs flushed.  That way instead of
taking the CACR default you'll take an MMU access error (since there are
no TLBs).

If I've misunderstood your problem please let me know.

--Kurt
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