Re: Coldfire 5235 I/D split cache

Hi Jate,

Jate Sujjavanich wrote:
> I also posted most of this on uClinux-dev. I am using a 2.4.31-uc0
> kernel.
> 
> I've been experimenting with enabling the split instruction and data
> cache on the 5235. I get a good speedup - my boot time is reduced by 30%
> to 27 seconds. However, I am occasionally getting problems with certain
> programs starting up (perhaps a pthreads issue). Things have worked
> perfectly when in i-cache only.
> 
> So does anyone have the split I/D cache working fine on 5235?

I looked at it a while back on the 5275. Though I didn't have
enough time to make it all work right.

The linux-2.4.x cache control code is a little "simplistic" for
the ColdFire's. You need to look at both:

  linux-2.4.x/include/asm-m68knommu/pgalloc.h
  linux-2.4.x/arch/m68knommu/mm/memory.c

The linux-2.6.x code is a little cleaner, though probably
doesn't work perfectly on split caches either. Concentrate on

  linux-2.6.x/include/asm-m68knommu/cachectl.h
  linux-2.6.x/include/asm-m68knommu/mcfcache.h

Regards
Greg



> Also, the CPUSHL instruction documentation is vague. The CF Programmer's
> Reference says one thing, and the MCF5235 ref says another. They seem to
> suggest that the CPUSHL instruction address operand specifies the
> address within the cache line instead of address of the memory being
> cached. Anyone have more experience with this?
> 
> 
> - Jate S.
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Greg Ungerer  --  Principal Engineer        EMAIL:     [email protected]
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