Re: Harvard caches
nop head <[email protected]> Fri, 27 Feb 2009 09:28:51 +0000
| Newsgroups | gmane.comp.hardware.motorola.microcontrollers.coldfire |
|---|---|
| Message-ID | <[email protected]> |
--00163646be02cc906b0463e31866 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi Nicolas, Thanks very much for the detailed answer. I was worried that overlapping the caches would cause coherency problems, but thinking more about it that would only be the case when code was being written to, and a push of the data cache followed by invalidating the instruction cache should fix that. So if the SRAM can only contain either code or data but not both then table 7-2 in section 7.6 is of the MCF547x reference manual makes no sense as it says set RAMBAR[5-0] to 0x21 if the data contained in SRAM contains both code and data. Regards, Chris 2009/2/27 Nicolas Pinault <[email protected]> > Hi, > > Please, see my answer below. > >> I am moving some code from a MCF537x coldfire, which had a unified cache, >> to a MCF547x which has separate instruction and data caches. >> >> My code has lots of tables declared as const so that they go into the read >> only text section in flash, rather than the initialised data section in RAM. >> Does this mean that all my table accesses will miss the cache because they >> will be in the range for the instruction cache, but are not instruction >> fetches? >> >> Similarly I have a few instructions in my bss section, mainly jump >> instruction to redirect interrupts to the relevent device driver. Am I right >> in thinking that these will all be cache misses as well because they will be >> in the range of the data cache but are actually instruction fetches? >> >> Is there any way I can set up the caches to emulate a unified cache or do >> I have to rewrite all my code? >> > In MCF5407, there are 4 ACRx registers. > ACR0 and ACR1 are for data cache. > ACR2 and ACR3 are for instruction cache > > If you initialise ACR0 and ACR1 with the same value, data and instruction > caches cover the same address range. > > Here is the code I use to initialise cache : > // Invalidate the cache and disable it > SetMCF5407CACR (MCF5407_CACR_DCINVA); > SetMCF5407CACR (MCF5407_CACR_BCINVA); > SetMCF5407CACR (MCF5407_CACR_ICINVA); > SetMCF5407CACR (MCF5407_CACR_DCINVA | > MCF5407_CACR_BCINVA | > MCF5407_CACR_ICINVA );//| > //MCF5407_CACR_HSDIS); > // Setup ACRs so that if cache is turned on, > only SDRAM and Flash are cached > SetMCF5407ACR0 (MCF5407_ACR_BASE((INT32U)__SDRAM_START) | > // MCF5407_ACR_MASK(0x00FFFFFF) | // 16Mo > // MCF5407_ACR_MASK(0x01FFFFFF) | // 32Mo > MCF5407_ACR_MASK(0x03FFFFFF) | // 64Mo > // MCF5407_ACR_MASK(0x07FFFFFF) | // 128Mo > // MCF5407_ACR_MASK((INT32U)__HEAP_END - > (INT32U)__SDRAM_START) | // See size in link file > MCF5407_ACR_E | > // MCF5407_ACR_CM(0) | // Write-through > MCF5407_ACR_CM(1) | // Copyback > MCF5407_ACR_S(2)); > SetMCF5407ACR1 (0); > > SetMCF5407ACR2 (MCF5407_ACR_BASE((INT32U)__FLASH_START) | > MCF5407_ACR_MASK(0x00) | > MCF5407_ACR_E | > MCF5407_ACR_CM(0) | > MCF5407_ACR_S(2)); > > SetMCF5407ACR3 (0x00FFC060); // See errata > > // Enable and configure cache > SetMCF5407CACR ( > MCF5407_CACR_DEC | > MCF5407_CACR_DESB | > MCF5407_CACR_DDCM (2) | > MCF5407_CACR_BEC | > //MCF5407_CACR_HSDIS | > MCF5407_CACR_IEC | > MCF5407_CACR_DNFB //| > //// MCF5407_CACR_IDCM > ); > > In my case, data cache covers only SDRAM space and instruction cache cover > full address space (ACR MASK is 0). > If you want instruction and data cache to cover the same address range, set > ACR0 and ACR2 with the same value. > Note : SetMCF5407ACRx() and other functions are custom made functions very > dependent on the compiler. > >> >> Another thing I don't understand is the two 4K SRAMs. The manual says I >> need to specifiy whether they are connected to the instruction bus or the >> data bus,. but it also gives RAMBAR address space settings for both code and >> data. Can I mix code and data in these RAMS, and if so, which bus do I >> specify and how does it work if they are one the wrong bus for the access? >> >> MCF5407 has 2 internal RAM blocks. 4K each. There are 2 RAMBAR registers > (RAMBAR0 and RAMBAR1), one for each internal RAM block. > Each internal RAM block can be independently mapped anywhere in address > space modulo granularity trough RAMBARx. > An internal RAM block can be connected either on instruction bus or on data > bus NOT both. > That is, an internal RAM block can be used either for code or for data NOT > both. > If you configure an internal RAM block for data and you try to run code > from it, you will get an exception. Same thing with an internal RAM block > configure for instruction and accessed for data. > > > Hope this helps. > > Regards, > Nicolas > > TIA, Chris >> [email protected] Send a post to the list. [email protected] the list. >> [email protected] Join the list in digest mode. >> [email protected] Leave the list. >> > --- > [email protected] Send a post to the list. > [email protected] Join the list. > [email protected] Join the list in digest mode. > [email protected] Leave the list. > > --00163646be02cc906b0463e31866 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi Nicolas,<br>=A0=A0 Thanks very much for the detailed answer. I was worri= ed that overlapping the caches would cause coherency problems, but thinking= more about it that would only be the case when code was being written to, = and a push of the data cache followed by invalidating the instruction cache= should fix that.<br> <br>So if the SRAM can only contain either code or data but not both then t= able 7-2 in section 7.6 is of the MCF547x reference manual makes no sense a= s it says set RAMBAR[5-0] to 0x21 if the data contained in SRAM contains bo= th code and data.<br> <br>Regards, Chris<br><br><div class=3D"gmail_quote">2009/2/27 Nicolas Pina= ult <span dir=3D"ltr"><<a href=3D"mailto:[email protected]">nicolasp@aa= ton.com</a>></span><br><blockquote class=3D"gmail_quote" style=3D"border= -left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-lef= t: 1ex;"> Hi,<br> <br> Please, see my answer below.<div class=3D"Ih2E3d"><br> <blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, = 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> I am moving some code from a MCF537x coldfire, which had a unified cache, t= o a MCF547x which has separate instruction and data caches.<br> <br> My code has lots of tables declared as const so that they go into the read = only text section in flash, rather than the initialised data section in RAM= . Does this mean that all my table accesses will miss the cache because the= y will be in the range for the instruction cache, but are not instruction f= etches?<br> <br> Similarly I have a few instructions in my bss section, mainly jump instruct= ion to redirect interrupts to the relevent device driver. Am I right in thi= nking that these will all be cache misses as well because they will be in t= he range of the data cache but are actually instruction fetches?<br> <br> Is there any way I can set up the caches to emulate a unified cache or do I= have to rewrite all my code?<br> </blockquote></div> In MCF5407, there are 4 ACRx registers.<br> ACR0 and ACR1 are for data cache.<br> ACR2 and ACR3 are for instruction cache<br> <br> If you initialise ACR0 and ACR1 with the same value, data and instruction c= aches cover the same address range.<br> <br> Here is the code I use to initialise cache :<br> =A0 // Invalidate the cache and disable it<br> =A0 SetMCF5407CACR (MCF5407_CACR_DCINVA);<br> =A0 SetMCF5407CACR (MCF5407_CACR_BCINVA);<br> =A0 SetMCF5407CACR (MCF5407_CACR_ICINVA);<br> =A0 SetMCF5407CACR (MCF5407_CACR_DCINVA =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_BCINVA |<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_ICINVA =A0 =A0);//|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 //MCF5407_CACR_HSDIS);<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 // Setup ACRs so = that if cache is turned on, only SDRAM and Flash are cached<br> =A0 SetMCF5407ACR0 (MCF5407_ACR_BASE((INT32U)__SDRAM_START) |<br> // =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_ACR_MASK(0x00FFFFFF) | = =A0 =A0 =A0// 16Mo<br> // =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_ACR_MASK(0x01FFFFFF) | = =A0 =A0 =A0// 32Mo<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_MASK(0x03FFFFFF) | =A0 =A0= =A0// 64Mo<br> // =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_ACR_MASK(0x07FFFFFF) | = =A0 =A0 =A0// 128Mo<br> // =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_ACR_MASK((INT32U)__HEAP_E= ND - (INT32U)__SDRAM_START) | =A0// See size in link file<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_E =A0 =A0 =A0 =A0 =A0|<br> // =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_ACR_CM(0) =A0 =A0 =A0| = =A0 =A0 =A0 =A0// Write-through<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_CM(1) =A0 =A0 =A0| =A0 =A0= =A0 =A0// Copyback<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_S(2));<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SetMCF5407ACR1 (0);<br> <br> =A0 SetMCF5407ACR2 (MCF5407_ACR_BASE((INT32U)__FLASH_START) |<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_MASK(0x00) |<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_E =A0 =A0 =A0 =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_CM(0) =A0 =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_ACR_S(2));<br> <br> =A0 SetMCF5407ACR3 (0x00FFC060); =A0 =A0 =A0 =A0 =A0 =A0// See errata<br> <br> =A0 // Enable and configure cache<br> =A0 SetMCF5407CACR (<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_DEC =A0 =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_DESB =A0 =A0 |<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_DDCM (2) |<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_BEC =A0 =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 //MCF5407_CACR_HSDIS =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_IEC =A0 =A0 =A0|<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 MCF5407_CACR_DNFB =A0 =A0 //|<br> //// =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0MCF5407_CACR_IDCM<br> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 );<br> <br> In my case, data cache covers only SDRAM space and instruction cache cover = full address space (ACR MASK is 0).<br> If you want instruction and data cache to cover the same address range, set= ACR0 and ACR2 with the same value.<br> Note : SetMCF5407ACRx() and other functions are custom made functions very = dependent on the compiler.<div class=3D"Ih2E3d"><br> <blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, = 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> <br> Another thing I don't understand is the two 4K SRAMs. The manual says I= need to specifiy whether they are connected to the instruction bus or the = data bus,. but it also gives RAMBAR address space settings for both code an= d data. Can I mix code and data in these RAMS, and if so, which bus do I sp= ecify and how does it work if they are one the wrong bus for the access?<br= > <br> </blockquote></div> MCF5407 has 2 internal RAM blocks. 4K each. There are 2 RAMBAR registers (R= AMBAR0 and RAMBAR1), one for each internal RAM block.<br> Each internal RAM block can be independently mapped anywhere in address spa= ce modulo granularity trough RAMBARx.<br> An internal RAM block can be connected either on instruction bus or on data= bus NOT both.<br> That is, an internal RAM block can be used either for code or for data NOT = both.<br> If you configure an internal RAM block for data and you try to run code fro= m it, you will get an exception. Same thing with an internal RAM block conf= igure for instruction and accessed for data.<br> <br> <br> Hope this helps.<br> <br> Regards,<br> Nicolas<br> <br> <blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, = 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> TIA, Chris<br> <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire@wildric= e.com</a> Send a post to the list. <a href=3D"mailto:coldfire-join@wildrice= .com" target=3D"_blank">[email protected]</a> Join the list. <a hr= ef=3D"mailto:[email protected]" target=3D"_blank">coldfire-diges= [email protected]</a> Join the list in digest mode. <a href=3D"mailto:coldfire= [email protected]" target=3D"_blank">[email protected]</a> Leav= e the list. <br> </blockquote> ---<br> <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire@wildric= e.com</a> =A0 =A0 =A0 =A0 =A0 =A0 =A0Send a post to the list.<br> <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire-jo= [email protected]</a> =A0 =A0 =A0 =A0Join the list.<br> <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire-= [email protected]</a> =A0 =A0Join the list in digest mode.<br> <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire-l= [email protected]</a> =A0 =A0 Leave the list.<br> <br> </blockquote></div><br> [email protected]=09Send a post to the list. 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