Re: Harvard caches

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Hi David,
  Looks like our posts crossed. Yes this self modifing code is a couple of
decades old and was done to reduce interrupt latency. Since the processor is
now about 200 times faster I could rewrite it to use pointers.

Regards, Chris


2009/2/27 David Brown <[email protected]>

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>
> nop head wrote:
>
>> I am moving some code from a MCF537x coldfire, which had a unified cache,
>> to a MCF547x which has separate instruction and data caches.
>>
>> My code has lots of tables declared as const so that they go into the read
>> only text section in flash, rather than the initialised data section in RAM.
>> Does this mean that all my table accesses will miss the cache because they
>> will be in the range for the instruction cache, but are not instruction
>> fetches?
>>
>>
> Your table data will be read as data, and thus go in the data cache. The
> same applies to any other constant data that is generated along with the
> code (such as const values, strings, etc.).  Normally you would have your
> instruction cache range covering either all memory (probably the easiest),
> or all memory that can contain instructions.  Your data cache range should
> cover all memory except perhaps peripheral areas.
>
>  Similarly I have a few instructions in my bss section, mainly jump
>> instruction to redirect interrupts to the relevent device driver. Am I right
>> in thinking that these will all be cache misses as well because they will be
>> in the range of the data cache but are actually instruction fetches?
>>
>>
> Self-modifying code has been considered bad style for several decades. I
> don't know your particular code or the problem you are trying to solve, but
> as general advice you should try to use function pointers rather than jump
> instructions in your table.
>
> If you want to keep the jump instructions, your main problem is cache
> synchronisation (ranges should be fixed as I said above).  When you change
> one of these indirect jumps, that's a data write and the change goes to the
> data cache.  The instruction cache knows nothing about the change (they are
> not synchronised - synchronising costs a lot of logic and latency).  You
> have to flush the relevant line of the data cache to make sure the change is
> written out, then you must flush the matching line in the instruction cache
> to make sure that you don't have old values in the instruction cache.  As
> you can see, using pointers is much easier.
>
>  Is there any way I can set up the caches to emulate a unified cache or do
>> I have to rewrite all my code?
>>
>> Another thing I don't understand is the two 4K SRAMs. The manual says I
>> need to specifiy whether they are connected to the instruction bus or the
>> data bus,. but it also gives RAMBAR address space settings for both code and
>> data. Can I mix code and data in these RAMS, and if so, which bus do I
>> specify and how does it work if they are one the wrong bus for the access?
>>
>> TIA, Chris
>> [email protected] Send a post to the list. [email protected] the list.
>> [email protected] Join the list in digest mode.
>> [email protected] Leave the list.
>>
>
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Hi David,<br>=A0 Looks like our posts crossed. Yes this self modifing code =
is a couple of decades old and was done to reduce interrupt latency. Since =
the processor is now about 200 times faster I could rewrite it to use point=
ers.<br>
<br>Regards, Chris<br><br><br><div class=3D"gmail_quote">2009/2/27 David Br=
own <span dir=3D"ltr">&lt;<a href=3D"mailto:[email protected]">david@we=
stcontrol.com</a>&gt;</span><br><blockquote class=3D"gmail_quote" style=3D"=
border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; paddi=
ng-left: 1ex;">
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ered to show you the spam information X-SpamDetect: ****: 4.000000 GreyPass=
ed=3D1.0, DodgySource=3D2.0, SPF Default Fail=3D1.0<br>
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ass=3D"Ih2E3d"><br>
<br>
nop head wrote:<br>
<blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, =
204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
I am moving some code from a MCF537x coldfire, which had a unified cache, t=
o a MCF547x which has separate instruction and data caches.<br>
<br>
My code has lots of tables declared as const so that they go into the read =
only text section in flash, rather than the initialised data section in RAM=
. Does this mean that all my table accesses will miss the cache because the=
y will be in the range for the instruction cache, but are not instruction f=
etches?<br>

<br>
</blockquote>
<br></div>
Your table data will be read as data, and thus go in the data cache. The sa=
me applies to any other constant data that is generated along with the code=
 (such as const values, strings, etc.). =A0Normally you would have your ins=
truction cache range covering either all memory (probably the easiest), or =
all memory that can contain instructions. =A0Your data cache range should c=
over all memory except perhaps peripheral areas.<div class=3D"Ih2E3d">
<br>
<br>
<blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, =
204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Similarly I have a few instructions in my bss section, mainly jump instruct=
ion to redirect interrupts to the relevent device driver. Am I right in thi=
nking that these will all be cache misses as well because they will be in t=
he range of the data cache but are actually instruction fetches?<br>

<br>
</blockquote>
<br></div>
Self-modifying code has been considered bad style for several decades. I do=
n&#39;t know your particular code or the problem you are trying to solve, b=
ut as general advice you should try to use function pointers rather than ju=
mp instructions in your table.<br>

<br>
If you want to keep the jump instructions, your main problem is cache synch=
ronisation (ranges should be fixed as I said above). =A0When you change one=
 of these indirect jumps, that&#39;s a data write and the change goes to th=
e data cache. =A0The instruction cache knows nothing about the change (they=
 are not synchronised - synchronising costs a lot of logic and latency). =
=A0You have to flush the relevant line of the data cache to make sure the c=
hange is written out, then you must flush the matching line in the instruct=
ion cache to make sure that you don&#39;t have old values in the instructio=
n cache. =A0As you can see, using pointers is much easier.<br>

<br>
<blockquote class=3D"gmail_quote" style=3D"border-left: 1px solid rgb(204, =
204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><div class=3D"Ih2=
E3d">
Is there any way I can set up the caches to emulate a unified cache or do I=
 have to rewrite all my code?<br>
<br>
Another thing I don&#39;t understand is the two 4K SRAMs. The manual says I=
 need to specifiy whether they are connected to the instruction bus or the =
data bus,. but it also gives RAMBAR address space settings for both code an=
d data. Can I mix code and data in these RAMS, and if so, which bus do I sp=
ecify and how does it work if they are one the wrong bus for the access?<br=
>

<br>
TIA, Chris<br>
</div><div class=3D"Ih2E3d"><a href=3D"mailto:[email protected]" target=
=3D"_blank">[email protected]</a> Send a post to the list. <a href=3D"m=
ailto:[email protected]" target=3D"_blank">coldfire-join@wildrice.=
com</a> Join the list. <a href=3D"mailto:[email protected]" targ=
et=3D"_blank">[email protected]</a> Join the list in digest mode=
. <a href=3D"mailto:[email protected]" target=3D"_blank">coldfire=
[email protected]</a> Leave the list.<br>

</div></blockquote><div><div></div><div class=3D"Wj3C7c">
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</div></div></blockquote></div><br>

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