Re: Harvard caches
Nicolas Pinault <[email protected]> Fri, 27 Feb 2009 16:55:53 +0100
| Newsgroups | gmane.comp.hardware.motorola.microcontrollers.coldfire |
|---|---|
| Organization | AATON |
| Message-ID | <[email protected]> |
This is a multi-part message in MIME format. --------------070304030608060805060405 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit > Hi Nicolas, > Thanks very much for the detailed answer. I was worried that > overlapping the caches would cause coherency problems, but thinking > more about it that would only be the case when code was being written > to, and a push of the data cache followed by invalidating the > instruction cache should fix that. > > So if the SRAM can only contain either code or data but not both then > table 7-2 in section 7.6 is of the MCF547x reference manual makes no > sense as it says set RAMBAR[5-0] to 0x21 if the data contained in SRAM > contains both code and data. Yes and no. Bits [5-0] are the same for all chip-select configurations. CS0, CS1, FLASHBAR, RAMBAR... all use these bits. If you configure RAMBAR0 for data access and you try to execute code from it you will get an exception. If you configure RAMBAR0 for instruction access, connect to data bus, you will have another type of error. I'm not sure but I think it will hang the system by not having TA asserted. Coniguring RAMBARx for both data and instruction access can be useful if you want to switch RAM for code to data and vice versa. Nicolas > > Regards, Chris > > 2009/2/27 Nicolas Pinault <[email protected] <mailto:[email protected]>> > > Hi, > > Please, see my answer below. > > I am moving some code from a MCF537x coldfire, which had a > unified cache, to a MCF547x which has separate instruction and > data caches. > > My code has lots of tables declared as const so that they go > into the read only text section in flash, rather than the > initialised data section in RAM. Does this mean that all my > table accesses will miss the cache because they will be in the > range for the instruction cache, but are not instruction fetches? > > Similarly I have a few instructions in my bss section, mainly > jump instruction to redirect interrupts to the relevent device > driver. Am I right in thinking that these will all be cache > misses as well because they will be in the range of the data > cache but are actually instruction fetches? > > Is there any way I can set up the caches to emulate a unified > cache or do I have to rewrite all my code? > > In MCF5407, there are 4 ACRx registers. > ACR0 and ACR1 are for data cache. > ACR2 and ACR3 are for instruction cache > > If you initialise ACR0 and ACR1 with the same value, data and > instruction caches cover the same address range. > > Here is the code I use to initialise cache : > // Invalidate the cache and disable it > SetMCF5407CACR (MCF5407_CACR_DCINVA); > SetMCF5407CACR (MCF5407_CACR_BCINVA); > SetMCF5407CACR (MCF5407_CACR_ICINVA); > SetMCF5407CACR (MCF5407_CACR_DCINVA | > MCF5407_CACR_BCINVA | > MCF5407_CACR_ICINVA );//| > //MCF5407_CACR_HSDIS); > // Setup ACRs so that if cache is > turned on, only SDRAM and Flash are cached > SetMCF5407ACR0 (MCF5407_ACR_BASE((INT32U)__SDRAM_START) | > // MCF5407_ACR_MASK(0x00FFFFFF) | // 16Mo > // MCF5407_ACR_MASK(0x01FFFFFF) | // 32Mo > MCF5407_ACR_MASK(0x03FFFFFF) | // 64Mo > // MCF5407_ACR_MASK(0x07FFFFFF) | // 128Mo > // MCF5407_ACR_MASK((INT32U)__HEAP_END - > (INT32U)__SDRAM_START) | // See size in link file > MCF5407_ACR_E | > // MCF5407_ACR_CM(0) | // Write-through > MCF5407_ACR_CM(1) | // Copyback > MCF5407_ACR_S(2)); > SetMCF5407ACR1 (0); > > SetMCF5407ACR2 (MCF5407_ACR_BASE((INT32U)__FLASH_START) | > MCF5407_ACR_MASK(0x00) | > MCF5407_ACR_E | > MCF5407_ACR_CM(0) | > MCF5407_ACR_S(2)); > > SetMCF5407ACR3 (0x00FFC060); // See errata > > // Enable and configure cache > SetMCF5407CACR ( > MCF5407_CACR_DEC | > MCF5407_CACR_DESB | > MCF5407_CACR_DDCM (2) | > MCF5407_CACR_BEC | > //MCF5407_CACR_HSDIS | > MCF5407_CACR_IEC | > MCF5407_CACR_DNFB //| > //// MCF5407_CACR_IDCM > ); > > In my case, data cache covers only SDRAM space and instruction > cache cover full address space (ACR MASK is 0). > If you want instruction and data cache to cover the same address > range, set ACR0 and ACR2 with the same value. > Note : SetMCF5407ACRx() and other functions are custom made > functions very dependent on the compiler. > > > Another thing I don't understand is the two 4K SRAMs. The > manual says I need to specifiy whether they are connected to > the instruction bus or the data bus,. but it also gives RAMBAR > address space settings for both code and data. Can I mix code > and data in these RAMS, and if so, which bus do I specify and > how does it work if they are one the wrong bus for the access? > > MCF5407 has 2 internal RAM blocks. 4K each. There are 2 RAMBAR > registers (RAMBAR0 and RAMBAR1), one for each internal RAM block. > Each internal RAM block can be independently mapped anywhere in > address space modulo granularity trough RAMBARx. > An internal RAM block can be connected either on instruction bus > or on data bus NOT both. > That is, an internal RAM block can be used either for code or for > data NOT both. > If you configure an internal RAM block for data and you try to run > code from it, you will get an exception. Same thing with an > internal RAM block configure for instruction and accessed for data. > > > Hope this helps. > > Regards, > Nicolas > > TIA, Chris > [email protected] <mailto:[email protected]> Send a > post to the list. [email protected] > <mailto:[email protected]> Join the list. > [email protected] > <mailto:[email protected]> Join the list in digest > mode. [email protected] > <mailto:[email protected]> Leave the list. > > --- > [email protected] <mailto:[email protected]> > Send a post to the list. > [email protected] <mailto:[email protected]> > Join the list. > [email protected] <mailto:[email protected]> > Join the list in digest mode. > [email protected] <mailto:[email protected]> > Leave the list. > > > [email protected] Send a post to the list. > [email protected] Join the list. [email protected] > Join the list in digest mode. [email protected] Leave the list. --------------070304030608060805060405 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> <meta content="text/html;charset=ISO-8859-1" http-equiv="Content-Type"> </head> <body bgcolor="#ffffff" text="#000000"> <br> <blockquote cite="mid:[email protected]" type="cite">Hi Nicolas,<br> Thanks very much for the detailed answer. I was worried that overlapping the caches would cause coherency problems, but thinking more about it that would only be the case when code was being written to, and a push of the data cache followed by invalidating the instruction cache should fix that.<br> <br> So if the SRAM can only contain either code or data but not both then table 7-2 in section 7.6 is of the MCF547x reference manual makes no sense as it says set RAMBAR[5-0] to 0x21 if the data contained in SRAM contains both code and data.<br> </blockquote> Yes and no. Bits [5-0] are the same for all chip-select configurations. CS0, CS1, FLASHBAR, RAMBAR... all use these bits.<br> If you configure RAMBAR0 for data access and you try to execute code from it you will get an exception.<br> If you configure RAMBAR0 for instruction access, connect to data bus, you will have another type of error. I'm not sure but I think it will hang the system by not having TA asserted.<br> Coniguring RAMBARx for both data and instruction access can be useful if you want to switch RAM for code to data and vice versa.<br> <br> Nicolas<br> <br> <blockquote cite="mid:[email protected]" type="cite"><br> Regards, Chris<br> <br> <div class="gmail_quote">2009/2/27 Nicolas Pinault <span dir="ltr"><<a moz-do-not-send="true" href="mailto:[email protected]">[email protected]</a>></span><br> <blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">Hi,<br> <br> Please, see my answer below. <div class="Ih2E3d"><br> <blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> I am moving some code from a MCF537x coldfire, which had a unified cache, to a MCF547x which has separate instruction and data caches.<br> <br> My code has lots of tables declared as const so that they go into the read only text section in flash, rather than the initialised data section in RAM. Does this mean that all my table accesses will miss the cache because they will be in the range for the instruction cache, but are not instruction fetches?<br> <br> Similarly I have a few instructions in my bss section, mainly jump instruction to redirect interrupts to the relevent device driver. Am I right in thinking that these will all be cache misses as well because they will be in the range of the data cache but are actually instruction fetches?<br> <br> Is there any way I can set up the caches to emulate a unified cache or do I have to rewrite all my code?<br> </blockquote> </div> In MCF5407, there are 4 ACRx registers.<br> ACR0 and ACR1 are for data cache.<br> ACR2 and ACR3 are for instruction cache<br> <br> If you initialise ACR0 and ACR1 with the same value, data and instruction caches cover the same address range.<br> <br> Here is the code I use to initialise cache :<br> // Invalidate the cache and disable it<br> SetMCF5407CACR (MCF5407_CACR_DCINVA);<br> SetMCF5407CACR (MCF5407_CACR_BCINVA);<br> SetMCF5407CACR (MCF5407_CACR_ICINVA);<br> SetMCF5407CACR (MCF5407_CACR_DCINVA |<br> MCF5407_CACR_BCINVA |<br> MCF5407_CACR_ICINVA );//|<br> //MCF5407_CACR_HSDIS);<br> // Setup ACRs so that if cache is turned on, only SDRAM and Flash are cached<br> SetMCF5407ACR0 (MCF5407_ACR_BASE((INT32U)__SDRAM_START) |<br> // MCF5407_ACR_MASK(0x00FFFFFF) | // 16Mo<br> // MCF5407_ACR_MASK(0x01FFFFFF) | // 32Mo<br> MCF5407_ACR_MASK(0x03FFFFFF) | // 64Mo<br> // MCF5407_ACR_MASK(0x07FFFFFF) | // 128Mo<br> // MCF5407_ACR_MASK((INT32U)__HEAP_END - (INT32U)__SDRAM_START) | // See size in link file<br> MCF5407_ACR_E |<br> // MCF5407_ACR_CM(0) | // Write-through<br> MCF5407_ACR_CM(1) | // Copyback<br> MCF5407_ACR_S(2));<br> SetMCF5407ACR1 (0);<br> <br> SetMCF5407ACR2 (MCF5407_ACR_BASE((INT32U)__FLASH_START) |<br> MCF5407_ACR_MASK(0x00) |<br> MCF5407_ACR_E |<br> MCF5407_ACR_CM(0) |<br> MCF5407_ACR_S(2));<br> <br> SetMCF5407ACR3 (0x00FFC060); // See errata<br> <br> // Enable and configure cache<br> SetMCF5407CACR (<br> MCF5407_CACR_DEC |<br> MCF5407_CACR_DESB |<br> MCF5407_CACR_DDCM (2) |<br> MCF5407_CACR_BEC |<br> //MCF5407_CACR_HSDIS |<br> MCF5407_CACR_IEC |<br> MCF5407_CACR_DNFB //|<br> //// MCF5407_CACR_IDCM<br> );<br> <br> In my case, data cache covers only SDRAM space and instruction cache cover full address space (ACR MASK is 0).<br> If you want instruction and data cache to cover the same address range, set ACR0 and ACR2 with the same value.<br> Note : SetMCF5407ACRx() and other functions are custom made functions very dependent on the compiler. <div class="Ih2E3d"><br> <blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> <br> Another thing I don't understand is the two 4K SRAMs. The manual says I need to specifiy whether they are connected to the instruction bus or the data bus,. but it also gives RAMBAR address space settings for both code and data. Can I mix code and data in these RAMS, and if so, which bus do I specify and how does it work if they are one the wrong bus for the access?<br> <br> </blockquote> </div> MCF5407 has 2 internal RAM blocks. 4K each. There are 2 RAMBAR registers (RAMBAR0 and RAMBAR1), one for each internal RAM block.<br> Each internal RAM block can be independently mapped anywhere in address space modulo granularity trough RAMBARx.<br> An internal RAM block can be connected either on instruction bus or on data bus NOT both.<br> That is, an internal RAM block can be used either for code or for data NOT both.<br> If you configure an internal RAM block for data and you try to run code from it, you will get an exception. Same thing with an internal RAM block configure for instruction and accessed for data.<br> <br> <br> Hope this helps.<br> <br> Regards,<br> Nicolas<br> <br> <blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"> TIA, Chris<br> <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Send a post to the list. <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Join the list. <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Join the list in digest mode. <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Leave the list. <br> </blockquote> ---<br> <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Send a post to the list.<br> <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Join the list.<br> <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Join the list in digest mode.<br> <a moz-do-not-send="true" href="mailto:[email protected]" target="_blank">[email protected]</a> Leave the list.<br> <br> </blockquote> </div> <br> <a class="moz-txt-link-abbreviated" href="mailto:[email protected]">[email protected]</a> Send a post to the list. <a class="moz-txt-link-abbreviated" href="mailto:[email protected]">[email protected]</a> Join the list. <a class="moz-txt-link-abbreviated" href="mailto:[email protected]">[email protected]</a> Join the list in digest mode. <a class="moz-txt-link-abbreviated" href="mailto:[email protected]">[email protected]</a> Leave the list. </blockquote> </body> </html> [email protected] Send a post to the list. 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