RE: TPU3 PWM glitch?

Yes, that makes sense (now).  However, the solution only moves my problem.  Instead of the 550ns pulse on the first period after writing PWMHI the output is driven low immediately.  If the write to PWMHI occurs right after the rising edge I still get a narrow pulse.  Any other tricks?

Thanks,
Steve

-----Original Message-----
From: Eric McRae [mailto:[email protected]]
Sent: Thursday, August 04, 2005 12:02 PM
To: [email protected]
Subject: Re: [MPC500] TPU3 PWM glitch?


Ahh, that would make sense.  Since you are only writing to PWMHI (not 
issuing an HSR), the function doesn't detect the zeroed PWMHI until the 
end of the current PWM period.  For normal PWM, the function configures 
the channel hardware to set the output high at the end of the period and 
that's just what happens.  In your case though, the function then 
realizes that PWMHI is zero, and forces the output low.  The 550nS is 
the time taken from the match at the end of the period until the code 
runs and recognizes the special case.

I think if you want to avoid the little pulse, you'll have to accompany 
the  zero of PWMHI with an HSR  to re-initialize the function.

Schroeder, Steven A. wrote:

> We are already limiting our lowest non-zero duty cycle to 5%, or 
> 12.5us at 4kHz.  The PWM signal at this duty is solid.  When we drop 
> below this value, zero is written to PWMHI.  The first period (250us 
> after the last >5% pulse) with PWMHI=0 emits a 550ns pulse.  This 
> pulse is seen regardless of where in the 250us period the write occurs.

-- 
Eric McRae, Electro-Logic Machines, Inc.
511 Root St., Port Townsend WA, 98368
Phone/Fax: 360.379.0969, http://www.elmi.com




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