RE: PORESET and SWT

Peter,

The problem seems to be related to your software, i.e.
MCU initialization. 

When you are running your board with attached debugger
it executes some initializations in the MCU to allow
seamless debugging. Usually debuggers reprogram SYPCR
register (which is writable once) to disable watchdog,
sometimes also they program CS logic to allow the
external memories access. Also debuggers program ICTRL
register to define CPU serialization and show cycles -
for code tracers. (When debugger is attached to the
MCU 
ICTRL can not be changed by user code).

The debugger initialization code is customizable and
you can review it to see what you are missing in your
application software.

Regards
Alex.

--- "Peter Allen (Yahoo)" <[email protected]>
wrote:

> 1k pull ups on resets haven't resolved the problem. 
> I have notice a
> similar problem using our Axiom MPC566EVB only here
> the timeout is ~3
> seconds and I scope the CLKOUT @ 56MHz appears to be
> the same problem
> only the EVB has already locked at 56MHz rather than
> 20MHz.
>  
> Having read some other posts I noticed that when I
> use my debugger to
> force a reset inside the 7s window after a PORESET
> the device boots
> immediatly.  I also tried with the eval board and
> notice that same thing
> when using either SRESET or HRESET within the 3s
> window post PORESET.
> 
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf
> Of Dobbin Allan-r11834
> Sent: Monday, 1 August 2005 12:57 PM
> To: '[email protected]'
> Subject: RE: [MPC500] PORESET and SWT
> 
> 
> 7secs is the WDOG timeout if you're using a 20MHz
> crystal.  If you don't
> reset properly, the WDOG kicks in, everything is
> reset and things run OK
> after that.
> 
> What value of pull-up do you have on HRESET?  10K is
> too high (may be an
> errata).  The rise time is too slow and modclk, etc
> don't get sampled
> correctly.  Reduce the HREST PU to 1K or 2K and see
> if that solve sthe
> problem.
> 
> (Vijay - you should have posted your similar issue
> on the group.)
> 
> Allan
> 
> 
> This sounds like a problem very similar to one that
> someone else was
> having a month or two ago - it was someone from this
> group, but I don't
> think the emails string was actually posted on the
> site.  Perhaps they
> can reply.  I think their problem ended up being too
> high a pull up on
> one of the reset lines, possibly POR.  But that
> resulted in too slow a
> POR time - check the spec but yours seems OK.
> 
> What was happening was POR was asserting too fast,
> things weren't reset
> correctly including PLL locking, and sebveral
> seconds later the watchdog
> would kick in and provide an HRESET and things run
> fine afterwards. Try
> reducing the POR
> 
> Allan
> 
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf
> Of Peter Allen \(Yahoo\)
> Sent: Sunday, July 31, 2005 6:46 PM
> To: [email protected]
> Subject: RE: [MPC500] PORESET and SWT
> 
> 
> I have a revised problem.
> 
> At POR the PORESET is a sserted by the power supply
> (MC33998) ~22ms.  
> HRESET in negated
> SRESET is negated
> 
> ENGCLK (i didn't run CLKOUT from under the device)
> starts at 312.5kHz
> (or 20MHz/64) and then ~7s  later HRESET is asserted
> by the MPC566 and
> the device restarts and function correctly.  I can't
> find a reason for
> the problem.
> 
> Thanks
> 
> Peter Allen
> Haltech Design Engineer
> www.haltech.com <http://www.haltech.com/> 
> ph:  95252400
> fax: 95252991
> 
> 
> 
> 
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf
> Of Dobbin Allan-r11834
> Sent: Tuesday, 26 July 2005 11:29 PM
> To: '[email protected]'
> Subject: RE: [MPC500] PORESET and SWT
> 
> 
> On the Axiom board, it sounds liekt he POR time is
> not long enough, but
> I would have suspected that h/w to be correct.  Your
> other h/w is a bit
> of a mystery i.e. why the PIT wouldn't work but
> other clocks would.  Is
> it possible the wrong clock source has been selected
> for the timer?  As
> far as guessing your sysclk speed - look at the
> CLKOUT signal.
> 
> Allan
> 
> 
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf
> Of Peter Allen \(Yahoo\)
> Sent: Monday, July 25, 2005 8:49 PM
> To: [email protected]
> Subject: [MPC500] PORESET and SWT
> 
> 
> I just got some hardware back and can get code into
> flash.  The device
> comes out of reset but doesn't boot withou BDM
> intervention (ie.  I
> attach to code already on target and then use the
> reset command and the
> code starts running as expected).  I have also
> noticed that the PIT
> doesn't always start working but serial coms and TPU
> run ok and the SWT
> doesn't ever time out to cause a reset.
> 
> Things I know (I think):
> 
> device is operating at desired 56MHz since:
>      baud rate is tied to this.
>     TPU functions are producing the correct timing
> patterns.
> 
> I noticed that on my Axiom eval board when i used
> the POReset the code
> would not boot until the watchdog timer ran out and
> and then everything
> would work OK.  I I used the Hreset or Sreset the
> system would bot
> straight away (power is applied to the board at all
> times).
> 
> If anyone has some wisdom on this problem I would
> greatly appreciate the
> help
> 
> Peter Allen
> Haltech Design Engineer
> www.haltech.com <http://www.haltech.com/> 
> ph:  95252400
> fax: 95252991
> 
> 
> 
>
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