QADC only inputs on four channels?

Hello,

 

Has anyone ever seen this problem, where the A_QADC is configured to do
software triggered continuous scan of the 16 input channels (internal mux)
and only the first four channels actually work. The remaining 12 channels
don't seem to be doing the conversion or are not updating the parameter RAM.
The configuration looks like this:

 

/*.

    QADC_A Configuration

--------------------------------------------

    Clock frequency: 1.000 MHz, High clock period: 600.000 ns, Low clock
period: 400.000 ns

    Operation: QADC freeze: Stop 

               Low power mode: Disable, Trigger assignment: ETRIG1 to queue
1; ETRIG2 to queue 2 

               Multiplexing: Internal , Data space restrictions: Supervisor
only 

    PORTQA directions: Pin 0: Input , Pin 1: Input , Pin 2: Input , Pin 3:
Input 

                       Pin 4: Input , Pin 5: Input , Pin 6: Input , Pin 7:
Input 

    Queue 1: Mode: Software triggered continuous-scan , Single scan: Disable

    Queue 1 completion interrupt: Disable, Queue 1: Pause interrupt: Disable

             ISR name:  

    Queue 2: Mode: Disabled , Single scan: Disable

             Begining: 64, Resume: with the first CCW 

             Completion interrupt: Disable, Pause interrupt: Disable

             ISR name:  

.*/

#define QADC_A_CONFIG_REG                 0x4080

#define QADC_A_CONTROL_REG1               0x1100

 

/*.

    QADC_A command conversion table 0-31 Command Conversion Table 0-31

-------------------------------------------------------------------------

    CCW1: Channel: 1, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW2: Channel: 2, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW3: Channel: 3, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW4: Channel: 4, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW5: Channel: 5, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW6: Channel: 6, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW7: Channel: 7, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW8: Channel: 8, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW9: Channel: 9, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW10: Channel: 10, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW11: Channel: 11, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW12: Channel: 12, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW13: Channel: 13, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW14: Channel: 14, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW15: Channel: 15, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

    CCW16: Channel: 63, Input sample time: 2 x QCLK , Channel: Disable,
Bypass: Disable

 

.*/

#define QADC_A_CCW_0                      0x0000

#define QADC_A_CCW_1                      0x0001

#define QADC_A_CCW_2                      0x0002

#define QADC_A_CCW_3                      0x0003

#define QADC_A_CCW_4                      0x0004

#define QADC_A_CCW_5                      0x0005

#define QADC_A_CCW_6                      0x0006

#define QADC_A_CCW_7                      0x0007

#define QADC_A_CCW_8                      0x0008

#define QADC_A_CCW_9                      0x0009

#define QADC_A_CCW_10                     0x000a

#define QADC_A_CCW_11                     0x000b

#define QADC_A_CCW_12                     0x000c

#define QADC_A_CCW_13                     0x000d

#define QADC_A_CCW_14                     0x000e

#define QADC_A_CCW_15                     0x000f

#define QADC_A_CCW_16                     0x003f

#define QADC_A_CCW_17                     0x0000

#define QADC_A_CCW_18                     0x0000

#define QADC_A_CCW_19                     0x0000

#define QADC_A_CCW_20                     0x0000

#define QADC_A_CCW_21                     0x0000

#define QADC_A_CCW_22                     0x0000

#define QADC_A_CCW_23                     0x0000

#define QADC_A_CCW_24                     0x0000

#define QADC_A_CCW_25                     0x0000

#define QADC_A_CCW_26                     0x0000

#define QADC_A_CCW_27                     0x0000

#define QADC_A_CCW_28                     0x0000

#define QADC_A_CCW_29                     0x0000

#define QADC_A_CCW_30                     0x0000

#define QADC_A_CCW_31                     0x0000

 

Thanks for any insight you might be able to offer.

 

Regards,

 

Dave

 



[Non-text portions of this message have been removed]



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