RE: Help regarding UART

Hello,

 

My MPC555 clock is configured as shown below (20.0Mhz) and the Quickstart
EABI tool GCT gave me 0x41 for 9600 baud. One of my clock dividers must be
set higher causing this lower value.

 

Regards,

 

Dave

 

 

/*.

    USIUCLK Configuration

--------------------------------------------

    Normal mode clock: 20.000 MHz (Initial)

    Low power mode clock: 10.000 MHz

    VCO frequency: 20.000 MHz

 

    Lock clock: Disable

    LIMP mode : Disable

    Clock switching if the PLL loses lock during reset : Enable 

    Power management request : Enable 

    Checkstop reset : Disable

    VDDSRAM detector : Enable 

    Interrupt : Disable

    Lock  Low Power Modes: Disable

    Loss of lock reset : Disable

    Change of lock interrupt level: None 

 

    CLKOUT frequency: 20.000 MHz

    CLKOUT mode: Enabled, full strength 

    ENGCLK frequency: 0.313 MHz

    ENGCLK output mode: Enabled, full strength 

    PITRTCLK frequency: 256: 0.078 MHz

    TB frequency: OSCCLK: 1.250 MHz

    BUCLK in LIMP mode  : Disable

.*/

 

/*.

    QSMCM_SCI Configuration

--------------------------------------------

    SCI 1: Baud rate: 9615.385 Bd

           Receiver: Enable , Transmitter: Enable , Data frame length: 10
bit 

           parity: None , Idle detect: Long , Loop mode: Disable

           Receiver interrupt: Disable, Transmitter interrupt: Disable

           Idle interrupt: Disable, Transmitter complete interrupt: Disable

 

    SCI 2: Baud rate: 9615.385 Bd

           Receiver: Enable , Transmitter: Enable , Data frame length: 10
bit 

           Parity: None , Idle detect: Short , Loop mode: Disable

           Receiver interrupt: Disable, Transmitter interrupt: Disable

           Idle interrupt: Disable, Transmitter complete interrupt: Disable

 

    QSCI: Bottom-half empty interrupt: Disable, Bottom-half full interrupt:
Disable

          Top-half empty interrupt: Disable, Top-half full interrupt:
Disable

 

    ISR name:  , Interrupt level: 0

.*/

#define QSMCM_SCI1_CONTROL_REG0           0x0041

#define QSMCM_SCI1_CONTROL_REG1           0x100c

#define QSMCM_SCI2_CONTROL_REG0           0x0041

#define QSMCM_SCI2_CONTROL_REG1           0x000c

 

  _____  

From: [email protected] [mailto:[email protected]] On Behalf Of
Dees Randy-rsaf30
Sent: Monday, September 12, 2005 3:05 PM
To: '[email protected]'
Subject: RE: [MPC500] Help regarding UART

 

it appears that the listing in the application note was not updated
completely for the MPC500 and assumed a 16.67MHz clock source.

For a 40 MHz MPC500 processor, you would use 0x82 with the divide by 32
prescaler and 0x411 for the divide by 4 prescaler. or 0x32 if a 20 MHz clock
(default) is used with the default prescaler (32) and the IMB at default
half speed.. 

randy

> -----Original Message-----
> On Behalf Of G.V.Sasanka
> 
>      I am trying to get familiarised with UART, I was going 
> through AN2371 file in freescale webpage...in the example 
> provided in that file baud rate is 9600 and its is specified 
> in hex as 01B2 can someone explain me the bathematics behind 
> it i.e mathematics which related 01B2 to 9600 baud rate...


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