Re: mpc555 memory mapping

Randall,

Thanks. It's working! I've got the 555 at base address 0, dual mapping
is enabled, and interrupts are being properly handled with the table
in XRAM at physical address 0x400000. This is great. Now I can have
ETRE=IP=1 in both DEBUG and INTFLASH targets, and XRAM is at the same
address in both targets, which makes everything simpler. There had to
be a way, but finding it is another story. I've worked with the 683XX
family for many years, and as I often found with those devices, once
you understand how something works, the manual seems very clear.

Now, let's see if it all still works from internal flash...

Joe


--- In [email protected], "Randall Young" <ryoung@n...> wrote:
>
> 
> > Thanks for the info. Let me see if I understand this.
> >
> > 1) 555 base address = 0x000000
> > 2) XRAM mapped to 0x400000 on CS1
> > 3) ETRE=1,IP=1,OERC=0 --> smaller exception table at 0x000000
> > 4) When debugging, dual map address 0x000000 to 0x400000 (CS1)
> >
> > When interrupts occur, exception vector fetch from 0x000000+offset
> > will actually be from XRAM 0x400000+offset? This will work even if
> > internal flash is disabled?
> 
> Yes, that's right.  If memory serves, enabling dual mapping
automatically
> disables internal flash so no conflict is possible.
> 
> > That would be great. I have found another way to map the 555 and XRAM
> > to separate 4MB regions, but it requires different APPCONFIG.H and
> > EXCTABLE.ASM files for the DEBUG and INTFLASH targets, which is very
> > inconvenient. Do you use QUICKSTART?
> 
> No, we used a different tool chain and pretty much rolled all our
own code.
> That was a few years back, I had to look up where the DME bit was :)
> 
> Randall Young
> Senior Software Engineer
> NavCom Technology, Inc.
> A John Deere Company
> 
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