RE: PLL not locking

are you looking at the correct bit. the SPLS bit indicates that the PLL
is locked. SPLSS signals that the PLL has, at some time, lost lock.
SPLSS is not set if the loss of lock was due to an intended change in
the clock frequency (writing the MF or DIVF bits).
 
I assume that CLOCKOUT is 20 MHz.
 
also check the BUCS bit in the SCCR to determine of the clock source is
the PLL or the limp clock is the system clock.
 
randy 

	-----Original Message-----
	From: [email protected] [mailto:[email protected]] On
Behalf Of praks411
	
	
	Hi
	I'm using MPC566 in my board. The pin configuration of my board
is same 
	as the evaluation board of MPC566. I'm using 4 Mhz crystal
oscillator 
	and XFC 0.033 microfarad (same as used in evaluation board). I'm
able 
	to write internal flash using BDM port, but when i try to run
program, 
	the SPLSS bit in PLPRCR is not setting. I've checked the CLKOUT
signal 
	of both evaluation board and my board, the waveform is same. I
mean 
	noise level is same as the evaluation board. Please suggest
something 
	what could be the reason.
	



[Non-text portions of this message have been removed]



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