RE: Interrupt Masking

Sorry, hit sent before I meant to...

Interrupts from the modules (QADC, QSMCM, MIOS, etc) are classed as
external interrupts.  To enable these, you have to set MSR[EE] and
MSR[RI].  Use the EIE to simplify this i.e.  "mtspr EIE,r7" which sets
both bits.  Also write MSR[IP] as reqd. to specify vector base location.

You also write relevant bits in the SIMASK register for all interrupt
sources you want to enable.

For example, if you want SCI as a high priority interrupt at level 1,
set SIMASK[LVM1] and also QSMCM.QDSCI_IL.B.ILDSCI = 1.

Regards,
Allan

-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf
Of joydeep roy
Sent: Wednesday, March 15, 2006 9:00 AM
To: MPC500 MPC500
Subject: [MPC500] Interrupt Masking


Hi all
This is a small query regarding masking of some
interrupt level. In MPC565/MPC566 Reference
Manual,page no.6-34 there is a note that suggest that
"To mask interrupt sources, first set the core's
status register interrupt mask level to that of the
source being masked in SIMASK. Then, the SIMASK bit
can be masked."
Can anyone tell me exactly which bit has to be
processed in the MSR??

Any help is appreciated.
Thanks,
Joy

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