RE: Interrupt Masking
"Dobbin Allan-r11834" <[email protected]>
| Newsgroups | gmane.comp.hardware.motorola.microcontrollers |
|---|---|
| Message-ID | <4147ED8B92A864498825C07E53594E4AD48487@az33exm20.fsl.freescale.net> |
Interrupts from the modules (QADC, QSMCM, MIOS, etc) are classed as external interrupts. To enable these, you have to set MSR[EE] (also set MSR[IP] to specify vector base location) as well as -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of joydeep roy Sent: Wednesday, March 15, 2006 9:00 AM To: MPC500 MPC500 Subject: [MPC500] Interrupt Masking Hi all This is a small query regarding masking of some interrupt level. In MPC565/MPC566 Reference Manual,page no.6-34 there is a note that suggest that "To mask interrupt sources, first set the core's status register interrupt mask level to that of the source being masked in SIMASK. Then, the SIMASK bit can be masked." Can anyone tell me exactly which bit has to be processed in the MSR?? Any help is appreciated. Thanks, Joy __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ----------------------------------------------------------- To learn more about Freescale Microcontrollers, please visit http://www.freescale.com/mcu Yahoo! Groups Links ----------------------------------------------------------- To learn more about Freescale Microcontrollers, please visit http://www.freescale.com/mcu Yahoo! Groups Links <*> To visit your group on the web, go to: http://groups.yahoo.com/group/MPC500/ <*> To unsubscribe from this group, send an email to: [email protected] <*> Your use of Yahoo! Groups is subject to: http://docs.yahoo.com/info/terms/