RE: Regarding QADC of MPC565

1. The PowerPC Architecture allows software to be run in Supervisor
(full access) or User mode Limited access). This allows an operating
system to limit the capability of a particular process of crashing the
complete system (doesn't allow processes to access global resources). By
default after reset, the CPU is in supervisor mode and has complete
access to registers. You must intentionally switch from Supervisor to
User mode.
2. As Allen replied, 14 or 20 is the number of clocks for a single
channel conversion.
3. The conversion time is the same for all on ship channels.
4. The access time is the same for all channels from either the A or the
B ADC is doing the conversion.
5. you need to account for the settling time of the external
multiplexer.
 
randy
 

	-----Original Message-----
	From: [email protected] [mailto:[email protected]] On
Behalf Of harini m
	
	

	Hi every body,
	I have following doubts regarding QADC of MPC565
	1. What is the meaning of supervisor only data access? Here in
QADC MCR,TEST and Interrupt register are supervisor access only
register. So how can i set supervisor access mode in MPC565?
	2. For QADC Conversion to be complete it takes 14 or 28 QCLK
cycle. Is this time for each conversion are for all 40 Channel
conversion complete?
	3. In MPC565 extra added Anlog channels (AN80 to AN87 internal
Multiplexing). What will be conversion time for this Analog inputs?
	4. Is there any access time difference for both modules(A & B)
if it is accessing Analog channels of other modules?
	5. If I connected externally multiplexing analog channels. What
are the different factors effecting the conversion time? 
	
	Please clarify these doubts any body as early as possible. 
	
	Advance thanks.
	
	Regards
	Harini.M
	

	.
	
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