RE: Regarding QADC of MPC565

I can answer your first two questions:
 
1. Refer to MSR[PR] which controlls if the CPU is in user or supervisor
mode.  Out of reset, the CPU is in supervisor mode and has access to all
supervisor regsiters.
 
2. This is the time for a conversion on one channel.
 

	-----Original Message-----
	From: [email protected] [mailto:[email protected]] On
Behalf Of harini m
	Sent: Monday, June 19, 2006 9:59 AM
	To: mpc500 group
	Subject: [MPC500] Regarding QADC of MPC565
	
	

	Hi every body,
	I have following doubts regarding QADC of MPC565
	1. What is the meaning of supervisor only data access? Here in
QADC MCR,TEST and Interrupt register are supervisor access only
register. So how can i set supervisor access mode in MPC565?
	2. For QADC Conversion to be complete it takes 14 or 28 QCLK
cycle. Is this time for each conversion are for all 40 Channel
conversion complete?
	3. In MPC565 extra added Anlog channels (AN80 to AN87 internal
Multiplexing). What will be conversion time for this Analog inputs?
	4. Is there any access time difference for both modules(A & B)
if it is accessing Analog channels of other modules?
	5. If I connected externally multiplexing analog channels. What
are the different factors effecting the conversion time? 
	
	Please clarify these doubts any body as early as possible. 
	
	Advance thanks.
	
	Regards
	Harini.M
	
	
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