Flow-through vs. Pipelined SRAM

Hello,


Due to availability problems, we are evaluating a "pipelined sync SRAM" to connect to a MPC555 to store code (and data) for debugging purpose only.
Up to now we used a "flow-through sync SRAM" (Cypress CY7C1345) according to a Freescale Application Note.

The only difference with a "pipelined sync SRAM" Cypress CY7X1347 seems to be a latch in the later on the output data, thus increasing read data access by one clock - not a big deal for burst access, only 20% slower...


Is my analysis correct?


Thanks for your help.

Best regards.


Jean-Christophe MATHAE

CIRTEM
http://www.cirtem.com

bâtiment Pointe Bleue
20, voie l'Occitane
BP661
31319 LABEGE cedex
France


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