Re: Flow-through vs. Pipelined SRAM

> Hello,
>
>
> Due to availability problems, we are evaluating a "pipelined sync SRAM" to
connect to a MPC555 to store code (and data) for debugging purpose only.
> Up to now we used a "flow-through sync SRAM" (Cypress CY7C1345) according
to a Freescale Application Note.
>
> The only difference with a "pipelined sync SRAM" Cypress CY7X1347 seems to
be a latch in the later on the output data, thus increasing read data access
by one clock - not a big deal for burst access, only 20% slower...
>
>
> Is my analysis correct?
>
>

Yes, except that for random access it will be 50% slower (3 clocks instead
of 2).  Burst access is only used for reading instructions - data access is
always done as random access (AFAIK).

It's easy enough to test at startup if the device is pipeline or
flow-through (setup the chip selects guessing it is flow-through, do a
couple of writes then read back the same addresses.  Change the chip selects
to pipeline if necessary), so that your software will work no matter what
you mount.




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