RE: Memory mapping on MPC556

Refer to documentation on MSR[IP] - if this bit is set, the exception
table is moved from 0x0 to 0xfff00000 thus reset vector becomes
0xfff00000.  This is controlled by the reset configuration sources you
listed below i.e. DATA pins (RSTCONF is LOW) or internal FLASH shadow
word (RSTCONF is HIGH).
 
You have the BA field correct for your example - don't forget that in
PPC talk, bits 0-16 are the MSBs.  I'm not familiar with your part, but
here is a setting to try for a 16Mbyte memory with burst disabled and
assuming CS0 - I've guessed 32-bit mem and WEBS=1.
 
 USIU.OR0.R = 0xff000640; /* CS0 16Mbyte, 4 wait states */
 USIU.BR0.R = 0x00070123; /* set base address, 32-bit, read only, BE,
internal TA */

- Allan

________________________________

From: [email protected] [mailto:[email protected]] On Behalf
Of rkaufmanus
Sent: Wednesday, November 22, 2006 4:18 PM
To: [email protected]
Subject: [MPC500] Memory mapping on MPC556



Hello everyone,

I have a slight problem with the memory controller and debugging with
the PE Micro PKGPPCZ.
When I reset the CPU in debug mode, the PC is set to 0xFF?00100.

The ? is because I'm writing with Linux booted and cannot simply look
up the real value. Anyway, I do not think that the real value is so
important.
As internal EPROM of the CPU starts at 0x00000000, I am wondering why
this happens. The MPC manual says that the startup address is
determined by:
'* The external data bus pins DATA[0:31]
* An internal default constant (0x0000 0000)
* An internal NVM register value (CMFCFIG)'

So why does the PC stand at 0xFF?00100 instead of 0x00000100 after
going into debug mode/reset or a watchdog reset? When NOT debugging
the board, everything (nearly) works fine.

My second problem is, that I cannot access the external EPROM on the
board, because the memory controller seems to be configured in the
wrong way. The manual says: 'Memory Controller Base Registers 0,Bits
0-16. These bits are compared to the corresponding unmasked address
signals among
ADDR[0:16] to determine if a memory bank controlled by the memory
controller is being accessed
by an internal bus master.'
Why are the LOWER 16 address bits compared? If my external memory
should be mapped to e.g. 0x00070000, I would expect that bits 17-31
are compared and I would put 0x0007 into the BR0 BA bits?
Can anyone give me a hint how to configure the memory controller in
order to access an external AM29BL802CB flash EPROM?

Thanks and best regards, Rainer



 


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