Management of several interrupts in the same time

My question is related to the management of several interrupts in the same
time. I use a MPC860 (It may be the same problem for MPC500)

Thanks to the SIPEND register, I know that two external interrupts occurred
in the same time (IRQ1 and IRQ2, on falling edge). The one which has the
main priority is managed in a first time, because SIVEC indicates the
corresponding vector.

Problem :
When I clean the first interrupt in writing the corresponding bit to "1" in
the SIPEND register, the second bit which was indicating the second external
interrupt is cleaned too. So the second interrupt is never managed.

Have you ever seen this problem and do you know a way to correct it ?

Thank you ;)

(Excuse me for my poor english)
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