RE: Re: TouCAN too slow by 2X?

"Dobbin Allan-r11834" <[email protected]> Tue, 26 Jun 2007 11:41:02 -0700
Newsgroups gmane.comp.hardware.motorola.microcontrollers
Message-ID <4147ED8B92A864498825C07E53594E4A024D74D9@az33exm20.fsl.freescale.net>
I see Rick's reply but missed the question.  
 
If CAN is running at div 2, its unlikely to be anything with the EBDF
and clkout as that only effects the EBI interface.  Its more likely to
be the IMB divider - see the UMCR register for details.
 
- Allan

________________________________

From: [email protected] [mailto:[email protected]] On Behalf
Of Corey, Richard
Sent: Tuesday, June 26, 2007 12:56 PM
To: [email protected]
Subject: [MPC500] Re: TouCAN too slow by 2X?



Back then, I had missed a half-speed feature - I think were driving the
external bus at half-speed:

8.5.2 Clock Out (CLKOUT)
CLKOUT has the same frequency as the general system
clock (GCLK2_50). Unlike the main system clock
GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents
the external bus clock, and thus will be
one-half of the main system clock if the external bus is
running at half speed (EBDF = 0b01). The
CLKOUT frequency (system frequency) defaults to VCO/2.


With a 40 MHz clock, I used CANbus prescaler dividers of 2,4,8 or 16
and 20 Tq/bit for 1 MBPS, 500, 250 or 125.

With a 56 MHz clock, I think you need to get a factor of 7 into the
prescaler, i.e. bring 56 MHz down to 8 MHz, but can you still get 1
MBPS? 

Check the minimum allowable values of the segments, and where your
sample point needs to fall - these may not be legal or workable values,
but are a starting point:

divide by 7
56 --> 8 MHz ~ 125 ns
Want 8 Tq per bit

SynchSeg + (PROPSEG+1) + (PSEG1+1) + (PSEG2+1) = 
1 + 4 + 1 + 2 = 8 time quanta per bit

Rick Corey

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