Re: BL2100 Expansion headers (LCD) to add extra IOs

Hi Scott.

Thanks for the input.  Just wondering if you can see if my thinking on this is right.


Just to
make sure I got the general idea right.  I should setup PE7 as a strobe.  I
use a 74VHC574 (PE7 “And” with one address line as an enable so that PE7 going
off everytime I read or write will not trigger the 74VHC574 incorrectly) to
store data like the /CS and other functions for the two other chips I want to
control.  Then I Rd/WrPortE() to the external
IO at the address I want (using 2 of the address lines as the /IORD and /IOWR
that I do not have) to all reading and writing I need to chips and then setup or
clear the 74VHC574 for the next function etc.  Does that sound about right?  I
have not done it this way before although I can see how this would be
done.  Just wanted to see if this is the
right thinking ….

Timing is
the thing I am worried about.  Not sure if
I am over thinking this.  Will the 74VHC574 take the data from the external IO correctly and write to the output of
the 74VHC574 when the PE7 and one address bit go back up to “high”?  I am not sure if the data line data will hold
longer than the PE7 and one address bit going “high” to trigger the flip flops  The other chips I think are OK because I
control the /CS etc using the 74VHC574 which I call before then reading or
writing data to the chips themselves….

Thanks again for your help.

Stan




________________________________
 From: Scott Henion <[email protected]>
To: [email protected] 
Sent: Wednesday, March 27, 2013 10:28 PM
Subject: Re: [rabbit-semi] BL2100 Expansion headers (LCD) to add extra IOs
 

  
On 3/27/2013 10:09 AM, Stan Hsu wrote:

It sounds like you can not use the Aux IO, but use the A0-A3 address lines to indicate write and read and also which chip to read/write.  Then just use the PE7 to enable the corresponding chip?  AuxIO would do so much of the work for you so it is much easier to realize.
>
Again, there is no difference. If it had port B for address and port
    A for data and aux I/O, you still have the same issue of no /IORD or
    /IOWR line.

Aux I/O uses Port B for lower address lines and port A for data.
Regular external I/O  uses the address an data busses of the CPU.
The timing is about the same.

Once PE7 is set up for either the accesses are the same
    instructions. You can use RdPortE() and WrPortE() the same on
    either.

Just set up IB7CR for external I/O then use Rd/WrPortE() with
    addresses 0xe00X. X= A0-3. Exactly the same for aux I/O. 

Access times are the same either way. Speed will depend on SW. ASM
    will help. With Softools, I find I don't need much ASM for speed.

The only real difference is putting something directly on the data
    bus can lock up the CPU if chip selects and data enables are not
    right as you get a bus collision. The board takes care of this via a
    data buffer only enabled on PE7 or PE0 and /IORD. They also buffer
    A0-3 so you can't interfere with the CPU memory.



>
>In essence, it does not sound too bad but not sure.  
>
>
>
>Also afraid if the SW will interfere somehow with the existing board.
>
>
>
>
>
Should not unless you ignore PE7 as an enable, then it would
    interfere with the external I/O on PE0.



-- 
------------------------------------------ Scott G. Henion, Consultant
Web site: http://SHDesigns.org ------------------------------------------