CVS: msp430-libc/include/msp430 usi.h,NONE,1.1 sd16.h,1.5,1.6 timera.h,1.11,1.12 timerb.h,1.9,1.10

Steve Underwood <[email protected]>
Newsgroups gmane.comp.hardware.texas-instruments.msp430.gcc.cvs
Message-ID <[email protected]> 
Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv21360/msp430-libc/include/msp430

Modified Files:
	sd16.h timera.h timerb.h 
Added Files:
	usi.h 
Log Message:
New 20xx devices, the new USI module,  and a couple of fixes


--- NEW FILE: usi.h ---
#if !defined(__msp430_headers_usi_h__)
#define __msp430_headers_usi_h__

/* usi.h
 *
 * mspgcc project: MSP430 device headers
 * USI module header
 *
 * (c) 2005 by Steve Underwood <[email protected]>
 * Originally based in part on work by Texas Instruments Inc.
 *
 * $Id: usi.h,v 1.1 2005/10/02 13:27:30 coppice Exp $
 */

/* Switches:

*/

#define USICTL0_            0x0078      /* USI  Control Register 0 */
sfrb(USICTL0, USICTL0_);
#define USICTL1_            0x0079      /* USI  Control Register 1 */
sfrb(USICTL1, USICTL1_);
#define USICKCTL_           0x007A      /* USI  Clock Control Register */
sfrb(USICKCTL, USICKCTL_);
#define USICNT_             0x007B      /* USI  Bit Counter Register */
sfrb(USICNT, USICNT_);
#define USISRL_             0x007C      /* USI  Low Byte Shift Register */
sfrb(USISRL, USISRL_);
#define USISRH_             0x007D      /* USI  High Byte Shift Register */
sfrb(USISRH, USISRH_);
#define USICTL_             0x0078      /* USI  Control Register */
sfrw(USICTL, USICTL_);

#define USICCTL_            0x007A      /* USI  Clock and Counter Control Register */
sfrw(USICCTL, USICCTL_);

#define USISR_              0x007C      /* USI  Shift Register */
sfrw(USISR, USISR_);

#define USIPE7              (0x80)      /* USI  Port Enable Px.7 */
#define USIPE6              (0x40)      /* USI  Port Enable Px.6 */
#define USIPE5              (0x20)      /* USI  Port Enable Px.5 */
#define USILSB              (0x10)      /* USI  LSB first  1:LSB / 0:MSB */
#define USIMST              (0x08)      /* USI  Master Select  0:Slave / 1:Master */
#define USIGE               (0x04)      /* USI  General Output Enable Latch */
#define USIOE               (0x02)      /* USI  Output Enable */
#define USISWRST            (0x01)      /* USI  Software Reset */

#define USICKPH             (0x80)      /* USI  Sync. Mode: Clock Phase */
#define USII2C              (0x40)      /* USI  I2C Mode */ 
#define USISTTIE            (0x20)      /* USI  START Condition interrupt enable */
#define USIIE               (0x10)      /* USI  Counter Interrupt enable */
#define USIAL               (0x08)      /* USI  Arbitration Lost */
#define USISTP              (0x04)      /* USI  STOP Condition received */
#define USISTTIFG           (0x02)      /* USI  START Condition interrupt Flag */
#define USIIFG              (0x01)      /* USI  Counter Interrupt Flag */

#define USIDIV2             (0x80)      /* USI  Clock Divider 2 */
#define USIDIV1             (0x40)      /* USI  Clock Divider 1 */ 
#define USIDIV0             (0x20)      /* USI  Clock Divider 0 */
#define USISSEL2            (0x10)      /* USI  Clock Source Select 2 */
#define USISSEL1            (0x08)      /* USI  Clock Source Select 1 */
#define USISSEL0            (0x04)      /* USI  Clock Source Select 0 */
#define USICKPL             (0x02)      /* USI  Clock Polarity 0:Inactive=Low / 1:Inactive=High */
#define USISWCLK            (0x01)      /* USI  Software Clock */

#define USIDIV_0            (0x00)      /* USI  Clock Divider: 0 */
#define USIDIV_1            (0x20)      /* USI  Clock Divider: 1 */
#define USIDIV_2            (0x40)      /* USI  Clock Divider: 2 */
#define USIDIV_3            (0x60)      /* USI  Clock Divider: 3 */
#define USIDIV_4            (0x80)      /* USI  Clock Divider: 4 */
#define USIDIV_5            (0xA0)      /* USI  Clock Divider: 5 */
#define USIDIV_6            (0xC0)      /* USI  Clock Divider: 6 */
#define USIDIV_7            (0xE0)      /* USI  Clock Divider: 7 */

#define USISSEL_0           (0x00)      /* USI  Clock Source: 0 */
#define USISSEL_1           (0x04)      /* USI  Clock Source: 1 */
#define USISSEL_2           (0x08)      /* USI  Clock Source: 2 */
#define USISSEL_3           (0x0C)      /* USI  Clock Source: 3 */
#define USISSEL_4           (0x10)      /* USI  Clock Source: 4 */
#define USISSEL_5           (0x14)      /* USI  Clock Source: 5 */
#define USISSEL_6           (0x18)      /* USI  Clock Source: 6 */
#define USISSEL_7           (0x1C)      /* USI  Clock Source: 7 */

#define USISCLREL           (0x80)      /* USI  SCL Released */
#define USI16B              (0x40)      /* USI  16 Bit Shift Register Enable */ 
#define USIFGDC             (0x20)      /* USI  Interrupt Flag don't clear */
#define USICNT4             (0x10)      /* USI  Bit Count 4 */
#define USICNT3             (0x08)      /* USI  Bit Count 3 */
#define USICNT2             (0x04)      /* USI  Bit Count 2 */
#define USICNT1             (0x02)      /* USI  Bit Count 1 */
#define USICNT0             (0x01)      /* USI  Bit Count 0 */

#endif

Index: sd16.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/sd16.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -w -d -r1.5 -r1.6
--- sd16.h	21 Mar 2005 13:43:08 -0000	1.5
+++ sd16.h	2 Oct 2005 13:27:30 -0000	1.6
@@ -1,5 +1,5 @@
-#ifndef __msp430_headers_sd16_h
-#define __msp430_headers_sd16_h
+#if !defined(__msp430_headers_sd16_h__)
+#define __msp430_headers_sd16_h__
 
 /* sd16.h
  *
@@ -31,7 +31,7 @@
 #define SD16CONF0_          0x00B7      /* SD16 Internal Configuration Register 0 */
 sfrb(SD16CONF0, SD16CONF0_);
 #define SD16CONF1_          0x00BF      /* SD16 Internal Configuration Register 1 */
-sfrb(SD16CONF0, SD16CONF0_);
+sfrb(SD16CONF1, SD16CONF1_);
                                         /* Please use only the recommended settings */
 #endif
 

Index: timera.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timera.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -w -d -r1.11 -r1.12
--- timera.h	5 Sep 2005 13:04:47 -0000	1.11
+++ timera.h	2 Oct 2005 13:27:30 -0000	1.12
@@ -1,5 +1,5 @@
-#ifndef __msp430_headers_timera_h
-#define __msp430_headers_timera_h
+#if !defined(__msp430_headers_timera_h__)
+#define __msp430_headers_timera_h__
 
 /* timera.h
  *
@@ -113,7 +113,7 @@
 sfrw (TA1CCR4, TA1CCR4_);
 #endif
 
-#ifndef _GNU_ASSEMBLER_
+#if !defined(_GNU_ASSEMBLER_)
 /* Structured declaration */
 typedef struct {
   volatile unsigned

Index: timerb.h
===================================================================
RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timerb.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -w -d -r1.9 -r1.10
--- timerb.h	17 Aug 2005 14:28:46 -0000	1.9
+++ timerb.h	2 Oct 2005 13:27:30 -0000	1.10
@@ -1,5 +1,5 @@
-#ifndef __msp430_headers_timerb_h
-#define __msp430_headers_timerb_h
+#if !defined(__msp430_headers_timerb_h__)
+#define __msp430_headers_timerb_h__
 
 /* timerb.h
  *
@@ -22,14 +22,15 @@
 sfrw(TBIV,TBIV_);
 #define TBCTL_              0x0180  /* Timer B Control */
 sfrw(TBCTL,TBCTL_);
+#define TBR_                0x0190  /* Timer B */
+sfrw(TBR,TBR_);
+
 #define TBCCTL0_            0x0182  /* Timer B Capture/Compare Control 0 */
 sfrw(TBCCTL0,TBCCTL0_);
 #define TBCCTL1_            0x0184  /* Timer B Capture/Compare Control 1 */
 sfrw(TBCCTL1,TBCCTL1_);
 #define TBCCTL2_            0x0186  /* Timer B Capture/Compare Control 2 */
 sfrw(TBCCTL2,TBCCTL2_);
-#define TBR_                0x0190  /* Timer B */
-sfrw(TBR,TBR_);
 #define TBCCR0_             0x0192  /* Timer B Capture/Compare 0 */
 sfrw(TBCCR0,TBCCR0_);
 #define TBCCR1_             0x0194  /* Timer B Capture/Compare 1 */



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