CVS: msp430-libc/include/msp430 unified_clock_system.h, NONE, 1.1 timera.h, 1.14, 1.15 usci.h, 1.6, 1.7
"Chris Liechti" <[email protected]> Thu, 4 Jun 2009 21:55:20 +0000
| Newsgroups | gmane.comp.hardware.texas-instruments.msp430.gcc.cvs |
|---|---|
| Message-ID | <[email protected]> |
Update of /cvsroot/mspgcc/msp430-libc/include/msp430 In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv15863/include/msp430 Modified Files: timera.h usci.h Added Files: unified_clock_system.h Log Message: - add the registers for the unified clock system (unified_clock_system.h) and patches the ucsi.h, timera.h, signal.h, msp430x54xx.h and msp430x261x.h thanks to Gerald --- NEW FILE: unified_clock_system.h --- #ifndef __msp430_headers_unified_clock_system_h #define __msp430_headers_unified_clock_system_h /* unified_clock_system.h * * mspgcc project: MSP430 device headers * UNIFIED_CLOCK_SYSTEM module header * * (c) 2002 by S. Balling <[email protected]> * Originally based in part on work by Texas Instruments Inc. * * $Id: unified_clock_system.h,v 1.1 2009/06/04 21:55:18 cliechti Exp $ */ /* Switches: __MSP430_HAS_UCS__ */ #if defined(__MSP430_HAS_UCS__) #define UCSCTL0_ 0x0160 sfrw (UCSCTL0,UCSCTL0_); #define UCSCTL0_L_ 0x0160 sfrb (UCSCTL0_L,UCSCTL0_L_); #define UCSCTL0_H_ 0x0161 sfrb (UCSCTL0_H,UCSCTL0_H_); #define UCSCTL1_ 0x0162 sfrw (UCSCTL1,UCSCTL1_); #define UCSCTL1_L_ 0x0162 sfrb (UCSCTL1_L,UCSCTL1_L_); #define UCSCTL1_H_ 0x0163 sfrb (UCSCTL1_H,UCSCTL1_H_); #define UCSCTL2_ 0x0164 sfrw (UCSCTL2,UCSCTL2_); #define UCSCTL2_L_ 0x0164 sfrb (UCSCTL2_L,UCSCTL2_L_); #define UCSCTL2_H_ 0x0165 sfrb (UCSCTL2_H,UCSCTL2_H_); #define UCSCTL3_ 0x0166 sfrw (UCSCTL3,UCSCTL3_); #define UCSCTL3_L_ 0x0166 sfrb (UCSCTL3_L,UCSCTL3_L_); #define UCSCTL3_H_ 0x0167 sfrb (UCSCTL3_H,UCSCTL3_H_); #define UCSCTL4_ 0x0168 sfrw (UCSCTL4,UCSCTL4_); #define UCSCTL4_L_ 0x0168 sfrb (UCSCTL4_L,UCSCTL4_L_); #define UCSCTL4_H_ 0x0169 sfrb (UCSCTL4_H,UCSCTL4_H_); #define UCSCTL5_ 0x016A sfrw (UCSCTL5,UCSCTL5_); #define UCSCTL5_L_ 0x016A sfrb (UCSCTL5_L,UCSCTL5_L_); #define UCSCTL5_H_ 0x016B sfrb (UCSCTL5_H,UCSCTL5_H_); #define UCSCTL6_ 0x016C sfrw (UCSCTL6,UCSCTL6_); #define UCSCTL6_L_ 0x016C sfrb (UCSCTL6_L,UCSCTL6_L_); #define UCSCTL6_H_ 0x016D sfrb (UCSCTL6_H,UCSCTL6_H_); #define UCSCTL7_ 0x016E sfrw (UCSCTL7,UCSCTL7_); #define UCSCTL7_L_ 0x016E sfrb (UCSCTL7_L,UCSCTL7_L_); #define UCSCTL7_H_ 0x016F sfrb (UCSCTL7_H,UCSCTL7_H_); #define UCSCTL8_ 0x0170 sfrw (UCSCTL8,UCSCTL8_); #define UCSCTL8_L_ 0x0170 sfrb (UCSCTL8_L,UCSCTL8_L_); #define UCSCTL8_H_ 0x0171 sfrb (UCSCTL8_H,UCSCTL8_H_); /* UCSCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0002) /* RESERVED */ //#define RESERVED (0x0004) /* RESERVED */ #define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ #define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ #define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ #define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ #define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ #define DCO0 (0x0100) /* DCO TAP Bit : 0 */ #define DCO1 (0x0200) /* DCO TAP Bit : 1 */ #define DCO2 (0x0400) /* DCO TAP Bit : 2 */ #define DCO3 (0x0800) /* DCO TAP Bit : 3 */ #define DCO4 (0x1000) /* DCO TAP Bit : 4 */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0002) /* RESERVED */ //#define RESERVED (0x0004) /* RESERVED */ #define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ #define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ #define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ #define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ #define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL0 Control Bits */ //#define RESERVED (0x0001) /* RESERVED */ //#define RESERVED (0x0002) /* RESERVED */ //#define RESERVED (0x0004) /* RESERVED */ #define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ #define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ #define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ #define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ #define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL1 Control Bits */ #define DISMOD (0x0001) /* Disable Modulation */ #define DCOR (0x0002) /* DCO External Resistor Select */ //#define RESERVED (0x0004) /* RESERVED */ //#define RESERVED (0x0008) /* RESERVED */ #define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ #define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ #define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL1 Control Bits */ #define DISMOD_L (0x0001) /* Disable Modulation */ #define DCOR_L (0x0002) /* DCO External Resistor Select */ //#define RESERVED (0x0004) /* RESERVED */ //#define RESERVED (0x0008) /* RESERVED */ #define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ #define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ #define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL1 Control Bits */ //#define RESERVED (0x0004) /* RESERVED */ //#define RESERVED (0x0008) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ #define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ #define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ #define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ #define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ #define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ #define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ #define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ #define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ /* UCSCTL2 Control Bits */ #define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ #define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ #define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ #define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ #define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ #define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ #define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ #define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ #define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ #define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ #define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ #define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ #define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL2 Control Bits */ #define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ #define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ #define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ #define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ #define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ #define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ #define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ #define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL2 Control Bits */ #define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ #define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ #define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ #define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ #define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ //#define RESERVED (0x8000) /* RESERVED */ #define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ #define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ #define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ #define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ #define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ #define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ #define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ #define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ #define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ #define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ #define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ #define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ #define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ #define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ /* UCSCTL3 Control Bits */ #define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ #define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ #define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ #define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ #define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL3 Control Bits */ #define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ #define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ #define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ #define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ #define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL3 Control Bits */ //#define RESERVED (0x0008) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0100) /* RESERVED */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ #define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ #define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ #define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ #define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ #define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ #define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ #define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ #define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ #define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ #define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ #define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ #define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ #define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ #define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ #define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ #define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ #define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ #define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ #define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ #define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ #define SELREF__VLOCLK (0x0010) /* Multiply Selected Loop Freq. By VLOCLK */ #define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ #define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ /* UCSCTL4 Control Bits */ #define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ #define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ #define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ #define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ #define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ //#define RESERVED (0x0080) /* RESERVED */ #define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ #define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ #define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL4 Control Bits */ #define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ #define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ #define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ #define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ #define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL4 Control Bits */ //#define RESERVED (0x0008) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ #define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ #define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ #define SELM_0 (0x0000) /* MCLK Source Select 0 */ #define SELM_1 (0x0001) /* MCLK Source Select 1 */ #define SELM_2 (0x0002) /* MCLK Source Select 2 */ #define SELM_3 (0x0003) /* MCLK Source Select 3 */ #define SELM_4 (0x0004) /* MCLK Source Select 4 */ #define SELM_5 (0x0005) /* MCLK Source Select 5 */ #define SELM_6 (0x0006) /* MCLK Source Select 6 */ #define SELM_7 (0x0007) /* MCLK Source Select 7 */ #define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ #define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ #define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ #define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ #define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ #define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ #define SELS_0 (0x0000) /* SMCLK Source Select 0 */ #define SELS_1 (0x0010) /* SMCLK Source Select 1 */ #define SELS_2 (0x0020) /* SMCLK Source Select 2 */ #define SELS_3 (0x0030) /* SMCLK Source Select 3 */ #define SELS_4 (0x0040) /* SMCLK Source Select 4 */ #define SELS_5 (0x0050) /* SMCLK Source Select 5 */ #define SELS_6 (0x0060) /* SMCLK Source Select 6 */ #define SELS_7 (0x0070) /* SMCLK Source Select 7 */ #define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ #define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ #define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ #define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ #define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ #define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ #define SELA_0 (0x0000) /* ACLK Source Select 0 */ #define SELA_1 (0x0100) /* ACLK Source Select 1 */ #define SELA_2 (0x0200) /* ACLK Source Select 2 */ #define SELA_3 (0x0300) /* ACLK Source Select 3 */ #define SELA_4 (0x0400) /* ACLK Source Select 4 */ #define SELA_5 (0x0500) /* ACLK Source Select 5 */ #define SELA_6 (0x0600) /* ACLK Source Select 6 */ #define SELA_7 (0x0700) /* ACLK Source Select 7 */ #define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ #define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ #define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ #define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ #define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ #define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ /* UCSCTL5 Control Bits */ #define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ #define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ #define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ #define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ #define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ //#define RESERVED (0x0080) /* RESERVED */ #define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ #define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ #define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ //#define RESERVED (0x0800) /* RESERVED */ #define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ #define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ #define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL5 Control Bits */ #define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ #define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ #define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ //#define RESERVED (0x0008) /* RESERVED */ #define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ #define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ #define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL5 Control Bits */ //#define RESERVED (0x0008) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ #define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ #define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ //#define RESERVED (0x0800) /* RESERVED */ #define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ #define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ #define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ //#define RESERVED (0x8000) /* RESERVED */ #define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ #define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ #define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ #define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ #define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ #define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ #define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ #define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ #define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ #define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ #define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ #define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ #define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ #define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ #define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ #define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ #define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ #define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ #define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ #define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ #define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ #define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ #define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ #define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ #define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ #define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ #define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ #define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ #define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ #define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ #define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ #define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ #define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ #define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ #define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ #define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ #define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ #define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ #define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ #define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ #define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ #define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ #define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ #define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ #define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ #define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ #define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ #define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ #define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ #define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ #define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ #define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ #define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ #define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ #define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ #define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ /* UCSCTL6 Control Bits */ #define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ #define SMCLKOFF (0x0002) /* SMCLK Off */ #define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ #define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ #define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ #define XTS (0x0020) /* 1: Selects high-freq. oscillator */ #define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ #define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ #define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ #define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ //#define RESERVED (0x2000) /* RESERVED */ #define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ #define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ /* UCSCTL6 Control Bits */ #define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ #define SMCLKOFF_L (0x0002) /* SMCLK Off */ #define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ #define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ #define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ #define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ #define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ #define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ /* UCSCTL6 Control Bits */ #define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ //#define RESERVED (0x0200) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ #define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ //#define RESERVED (0x2000) /* RESERVED */ #define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ #define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ #define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ #define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ #define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ #define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ #define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ #define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ #define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ #define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ #define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ #define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ #define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ #define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ /* UCSCTL7 Control Bits */ #define DCOFFG (0x0001) /* DCO Fault Flag */ #define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ #define XT1HFOFFG (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ #define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ #define FLLULIFG (0x0010) /* FLL Unlock Interrupt Flag */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define FLLUNLOCK0 (0x0100) /* FLL Unlock Bit 0 */ #define FLLUNLOCK1 (0x0200) /* FLL Unlock Bit 1 */ #define FLLUNLOCKHIS0 (0x0400) /* FLL Unlock History Bit 0 */ #define FLLUNLOCKHIS1 (0x08000) /* FLL Unlock History Bit 1 */ #define FLLULIE (0x01000) /* FLL Unlock Interrupt Enable */ #define FLLWARNEN (0x02000) /* FLL Warning Enable */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL7 Control Bits */ #define DCOFFG_L (0x0001) /* DCO Fault Flag */ #define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ #define XT1HFOFFG_L (0x0004) /* XT1 High Frequency Oscillator 1 Fault Flag */ #define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ #define FLLULIFG_L (0x0010) /* FLL Unlock Interrupt Flag */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL7 Control Bits */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define FLLUNLOCK0_H (0x0001) /* FLL Unlock Bit 0 */ #define FLLUNLOCK1_H (0x0002) /* FLL Unlock Bit 1 */ #define FLLUNLOCKHIS0_H (0x0004) /* FLL Unlock History Bit 0 */ #define FLLUNLOCKHIS1_H (0x0080) /* FLL Unlock History Bit 1 */ #define FLLULIE_H (0x0010) /* FLL Unlock Interrupt Enable */ #define FLLWARNEN_H (0x0020) /* FLL Warning Enable */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL8 Control Bits */ #define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ #define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ #define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ #define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ #define IFCLKSEN (0x0010) /* Enable Interface Clock slow down mechanism */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define SMCLK_FSEN (0x0100) /* Enable fail safe enable for SMCLK source */ #define ACLK_FSEN (0x0200) /* Enable fail safe enable for ACLK source */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL8 Control Bits */ #define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ #define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ #define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ #define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ #define IFCLKSEN_L (0x0010) /* Enable Interface Clock slow down mechanism */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ /* UCSCTL8 Control Bits */ //#define RESERVED (0x0020) /* RESERVED */ //#define RESERVED (0x0040) /* RESERVED */ //#define RESERVED (0x0080) /* RESERVED */ #define SMCLK_FSEN_H (0x0001) /* Enable fail safe enable for SMCLK source */ #define ACLK_FSEN_H (0x0002) /* Enable fail safe enable for ACLK source */ //#define RESERVED (0x0400) /* RESERVED */ //#define RESERVED (0x0800) /* RESERVED */ //#define RESERVED (0x1000) /* RESERVED */ //#define RESERVED (0x2000) /* RESERVED */ //#define RESERVED (0x4000) /* RESERVED */ //#define RESERVED (0x8000) /* RESERVED */ #endif #endif /*__msp430_headers_unified_clock_system_h */ Index: timera.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/timera.h,v retrieving revision 1.14 retrieving revision 1.15 diff -u -w -d -r1.14 -r1.15 --- timera.h 9 Oct 2008 15:00:14 -0000 1.14 +++ timera.h 4 Jun 2009 21:55:18 -0000 1.15 @@ -9,6 +9,10 @@ * (c) 2002 by M. P. Ashton <[email protected]> * Originally based in part on work by Texas Instruments Inc. * + * 2009-05-19 - modifications by S. Balling <[email protected]> + * - added T0A5 + * - added T1A3 + * * $Id$ */ @@ -18,9 +22,161 @@ __MSP430_HAS_TA3__ - if the device has a timer0 A with 3 channels __MSP430_HAS_T1A2__ - if the device has a timer1 A with 2 channels, as well as timer0 A __MSP430_HAS_T1A5__ - if the device has a timer1 A with 5 channels, as well as timer0 A +__MSP430_HAS_T0A5__ - if the device has a timer0 A with 5 channels +__MSP430_HAS_T1A3__ - if the device has a timer1 A with 3 channels */ +#if defined(__MSP430_HAS_T0A5__) +#define TA0CTL_ 0x0340 +sfrw (TA0CTL,TA0CTL_); +#define TA0CTL_L_ 0x0340 +sfrb (TA0CTL_L,TA0CTL_L_); +#define TA0CTL_H_ 0x0341 +sfrb (TA0CTL_H,TA0CTL_H_); +#define TA0CCTL0_ 0x0342 +sfrw (TA0CCTL0,TA0CCTL0_); +#define TA0CCTL0_L_ 0x0342 +sfrb (TA0CCTL0_L,TA0CCTL0_L_); +#define TA0CCTL0_H_ 0x0343 +sfrb (TA0CCTL0_H,TA0CCTL0_H_); +#define TA0CCTL1_ 0x0344 +sfrw (TA0CCTL1,TA0CCTL1_); +#define TA0CCTL1_L_ 0x0344 +sfrb (TA0CCTL1_L,TA0CCTL1_L_); +#define TA0CCTL1_H_ 0x0345 +sfrb (TA0CCTL1_H,TA0CCTL1_H_); +#define TA0CCTL2_ 0x0346 +sfrw (TA0CCTL2,TA0CCTL2_); +#define TA0CCTL2_L_ 0x0346 +sfrb (TA0CCTL2_L,TA0CCTL2_L_); +#define TA0CCTL2_H_ 0x0347 +sfrb (TA0CCTL2_H,TA0CCTL2_H_); +#define TA0CCTL3_ 0x0348 +sfrw (TA0CCTL3,TA0CCTL3_); +#define TA0CCTL3_L_ 0x0348 +sfrb (TA0CCTL3_L,TA0CCTL3_L_); +#define TA0CCTL3_H_ 0x0349 +sfrb (TA0CCTL3_H,TA0CCTL3_H_); +#define TA0CCTL4_ 0x034A +sfrw (TA0CCTL4,TA0CCTL4_); +#define TA0CCTL4_L_ 0x034A +sfrb (TA0CCTL4_L,TA0CCTL4_L_); +#define TA0CCTL4_H_ 0x034B +sfrb (TA0CCTL4_H,TA0CCTL4_H_); +#define TA0R_ 0x0350 +sfrw (TA0R,TA0R_); +#define TA0R_L_ 0x0350 +sfrb (TA0R_L,TA0R_L_); +#define TA0R_H_ 0x0351 +sfrb (TA0R_H,TA0R_H_); +#define TA0CCR0_ 0x0352 +sfrw (TA0CCR0,TA0CCR0_); +#define TA0CCR0_L_ 0x0352 +sfrb (TA0CCR0_L,TA0CCR0_L_); +#define TA0CCR0_H_ 0x0353 +sfrb (TA0CCR0_H,TA0CCR0_H_); +#define TA0CCR1_ 0x0354 +sfrw (TA0CCR1,TA0CCR1_); +#define TA0CCR1_L_ 0x0354 +sfrb (TA0CCR1_L,TA0CCR1_L_); +#define TA0CCR1_H_ 0x0355 +sfrb (TA0CCR1_H,TA0CCR1_H_); +#define TA0CCR2_ 0x0356 +sfrw (TA0CCR2,TA0CCR2_); +#define TA0CCR2_L_ 0x0356 +sfrb (TA0CCR2_L,TA0CCR2_L_); +#define TA0CCR2_H_ 0x0357 +sfrb (TA0CCR2_H,TA0CCR2_H_); +#define TA0CCR3_ 0x0358 +sfrw (TA0CCR3,TA0CCR3_); +#define TA0CCR3_L_ 0x0358 +sfrb (TA0CCR3_L,TA0CCR3_L_); +#define TA0CCR3_H_ 0x0359 +sfrb (TA0CCR3_H,TA0CCR3_H_); +#define TA0CCR4_ 0x035A +sfrw (TA0CCR4,TA0CCR4_); +#define TA0CCR4_L_ 0x035A +sfrb (TA0CCR4_L,TA0CCR4_L_); +#define TA0CCR4_H_ 0x035B +sfrb (TA0CCR4_H,TA0CCR4_H_); +#define TA0IV_ 0x036E +sfrw (TA0IV,TA0IV_); +#define TA0IV_L_ 0x036E +sfrb (TA0IV_L,TA0IV_L_); +#define TA0IV_H_ 0x036F +sfrb (TA0IV_H,TA0IV_H_); +#define TA0EX0_ 0x0360 +sfrw (TA0EX0,TA0EX0_); +#define TA0EX0_L_ 0x0360 +sfrb (TA0EX0_L,TA0EX0_L_); +#define TA0EX0_H_ 0x0361 +sfrb (TA0EX0_H,TA0EX0_H_); +#endif /* __MSP430_HAS_T0A5__ */ + +#if defined(__MSP430_HAS_T1A3__) +#define TA1CTL_ 0x0380 +sfrw (TA1CTL,TA1CTL_); +#define TA1CTL_L_ 0x0380 +sfrb (TA1CTL_L,TA1CTL_L_); +#define TA1CTL_H_ 0x0381 +sfrb (TA1CTL_H,TA1CTL_H_); +#define TA1CCTL0_ 0x0382 +sfrw (TA1CCTL0,TA1CCTL0_); +#define TA1CCTL0_L_ 0x0382 +sfrb (TA1CCTL0_L,TA1CCTL0_L_); +#define TA1CCTL0_H_ 0x0383 +sfrb (TA1CCTL0_H,TA1CCTL0_H_); +#define TA1CCTL1_ 0x0384 +sfrw (TA1CCTL1,TA1CCTL1_); +#define TA1CCTL1_L_ 0x0384 +sfrb (TA1CCTL1_L,TA1CCTL1_L_); +#define TA1CCTL1_H_ 0x0385 +sfrb (TA1CCTL1_H,TA1CCTL1_H_); +#define TA1CCTL2_ 0x0386 +sfrw (TA1CCTL2,TA1CCTL2_); +#define TA1CCTL2_L_ 0x0386 +sfrb (TA1CCTL2_L,TA1CCTL2_L_); +#define TA1CCTL2_H_ 0x0387 +sfrb (TA1CCTL2_H,TA1CCTL2_H_); +#define TA1R_ 0x0390 +sfrw (TA1R,TA1R_); +#define TA1R_L_ 0x0390 +sfrb (TA1R_L,TA1R_L_); +#define TA1R_H_ 0x0391 +sfrb (TA1R_H,TA1R_H_); +#define TA1CCR0_ 0x0392 +sfrw (TA1CCR0,TA1CCR0_); +#define TA1CCR0_L_ 0x0392 +sfrb (TA1CCR0_L,TA1CCR0_L_); +#define TA1CCR0_H_ 0x0393 +sfrb (TA1CCR0_H,TA1CCR0_H_); +#define TA1CCR1_ 0x0394 +sfrw (TA1CCR1,TA1CCR1_); +#define TA1CCR1_L_ 0x0394 +sfrb (TA1CCR1_L,TA1CCR1_L_); +#define TA1CCR1_H_ 0x0395 +sfrb (TA1CCR1_H,TA1CCR1_H_); +#define TA1CCR2_ 0x0396 +sfrw (TA1CCR2,TA1CCR2_); +#define TA1CCR2_L_ 0x0396 +sfrb (TA1CCR2_L,TA1CCR2_L_); +#define TA1CCR2_H_ 0x0397 +sfrb (TA1CCR2_H,TA1CCR2_H_); +#define TA1IV_ 0x03AE +sfrw (TA1IV,TA1IV_); +#define TA1IV_L_ 0x03AE +sfrb (TA1IV_L,TA1IV_L_); +#define TA1IV_H_ 0x03AF +sfrb (TA1IV_H,TA1IV_H_); +#define TA1EX0_ 0x03A0 +sfrw (TA1EX0,TA1EX0_); +#define TA1EX0_L_ 0x03A0 +sfrb (TA1EX0_L,TA1EX0_L_); +#define TA1EX0_H_ 0x03A1 +sfrb (TA1EX0_H,TA1EX0_H_); +#endif /* __MSP430_HAS_T1A3__ */ + #if defined(__MSP430_HAS_TA2__) || defined(__MSP430_HAS_TA3__) #define TA0IV_ 0x012E /* Timer A 0 Interrupt Vector Word */ sfrw (TA0IV,TA0IV_); Index: usci.h =================================================================== RCS file: /cvsroot/mspgcc/msp430-libc/include/msp430/usci.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -w -d -r1.6 -r1.7 --- usci.h 18 Jun 2008 22:25:52 -0000 1.6 +++ usci.h 4 Jun 2009 21:55:18 -0000 1.7 @@ -14,11 +14,21 @@ * 2008-02-05 - modifications by G.Lemm <[email protected]> * - added UC1IE and UC1IFG registers * - added UC*1*IE and UC*1*IFG bit definitions + * 2009-05-19 - modifications by S. Balling <[email protected]> + * - added switch for USCI0 + * - added USCI0_5 + * - added USCI1_5 + * - added USCI2_5 + * - added USCI3_5 */ /* Switches: - +__MSP430_HAS_USCI0__ - if device has USCI0 __MSP430_HAS_USCI1__ - if device has USCI1 +__MSP430_HAS_USCI0_5__ - if device has USCI0 and is part of family 5 +__MSP430_HAS_USCI1_5__ - if device has USCI1 and is part of family 5 +__MSP430_HAS_USCI2_5__ - if device has USCI2 and is part of family 5 +__MSP430_HAS_USCI3_5__ - if device has USCI3 and is part of family 5 */ @@ -246,6 +256,8 @@ #define UCSSEL_ACLK UCSSEL_1 #define UCSSEL_SMCLK UCSSEL_2 +#if defined(__MSP430_HAS_USCI0__) + /* -------- USCI0 */ #define UCA0CTL0_ 0x0060 /* USCI A0 Control Register 0 */ @@ -291,6 +303,7 @@ sfrw(UCB0I2COA, UCB0I2COA_); #define UCB0I2CSA_ 0x011A /* USCI B0 I2C Slave Address */ sfrw(UCB0I2CSA, UCB0I2CSA_); +#endif /* __MSP430_HAS_USCI0__ */ #if defined(__MSP430_HAS_USCI1__) @@ -356,4 +369,331 @@ #define UCB1TXIFG (1<<3) #endif /* __MSP430_HAS_USCI1__ */ +#if defined(__MSP430_HAS_USCI0_5__) + +/* -------- USCI0_5 */ + +#define UCA0CTL0_ 0x05C1 +sfrb(UCA0CTL0, UCA0CTL0_); +#define UCA0CTL1_ 0x05C0 +sfrb(UCA0CTL1, UCA0CTL1_); +#define UCA0BR0_ 0x05C6 +sfrb(UCA0BR0, UCA0BR0_); +#define UCA0BR1_ 0x05C7 +sfrb(UCA0BR1, UCA0BR1_); +#define UCA0MCTL_ 0x05C8 +sfrb(UCA0MCTL, UCA0MCTL_); +#define UCA0STAT_ 0x05CA +sfrb(UCA0STAT, UCA0STAT_); +#define UCA0RXBUF_ 0x05CC +sfrb(UCA0RXBUF, UCA0RXBUF_); +#define UCA0TXBUF_ 0x05CE +sfrb(UCA0TXBUF, UCA0TXBUF_); +#define UCA0ABCTL_ 0x05D0 +sfrb(UCA0ABCTL, UCA0ABCTL_); +#define UCA0IRTCTL_ 0x05D2 +sfrb(UCA0IRTCTL, UCA0IRTCTL_); +#define UCA0IRRCTL_ 0x05D3 +sfrb(UCA0IRRCTL, UCA0IRRCTL_); +#define UCA0IE_ 0x05DC +sfrb(UCA0IE, UCA0IE_); +#define UCA0IFG_ 0x05DD +sfrb(UCA0IFG, UCA0IFG_); +#define UCA0IV_ 0x05DE +sfrw(UCA0IV, UCA0IV_); +#define UCA0IV_L_ 0x05DE +sfrb(UCA0IV_L, UCA0IV_L_); +#define UCA0IV_H_ 0x05DF +sfrb(UCA0IV_H, UCA0IV_H_); + +#define UCB0CTL0_ 0x05E1 +sfrb(UCB0CTL0, UCB0CTL0_); +#define UCB0CTL1_ 0x05E0 +sfrb(UCB0CTL1, UCB0CTL1_); +#define UCB0BR0_ 0x05E6 +sfrb(UCB0BR0, UCB0BR0_); +#define UCB0BR1_ 0x05E7 +sfrb(UCB0BR1, UCB0BR1_); +#define UCB0MCTL_ 0x05E8 +sfrb(UCB0MCTL, UCB0MCTL_); +#define UCB0STAT_ 0x05EA +sfrb(UCB0STAT, UCB0STAT_); +#define UCB0RXBUF_ 0x05EC +sfrb(UCB0RXBUF, UCB0RXBUF_); +#define UCB0TXBUF_ 0x05EE +sfrb(UCB0TXBUF, UCB0TXBUF_); +#define UCB0I2COA_ 0x05F0 +sfrb(UCB0I2COA, UCB0I2COA_); +#define UCB0I2CSA_ 0x05F2 +sfrb(UCB0I2CSA, UCB0I2CSA_); +#define UCB0IE_ 0x05FC +sfrb(UCB0IE, UCB0IE_); +#define UCB0IFG_ 0x05FD +sfrb(UCB0IFG, UCB0IFG_); +#define UCB0IV_ 0x05FE +sfrw(UCB0IV, UCB0IV_); +#define UCB0IV_L_ 0x05FE +sfrb(UCB0IV_L, UCB0IV_L_); +#define UCB0IV_H_ 0x05FF +sfrb(UCB0IV_H, UCB0IV_H_); + +#endif /* __MSP430_HAS_USCI0_5__ */ + +#if defined(__MSP430_HAS_USCI1_5__) + +/* -------- USCI1_5 */ + +// tbd +/*#define UCA1CTL0_ 0x0601 +#define UCA1CTL0_L 0x0601 +#define UCA1CTL0_H 0x0602 +#define UCA1CTL1_ 0x0600 +#define UCA1CTL1_L 0x0600 +#define UCA1CTL1_H 0x0601 +#define UCA1BR0_ 0x0606 +#define UCA1BR0_L 0x0606 +#define UCA1BR0_H 0x0607 +#define UCA1BR1_ 0x0607 +#define UCA1BR1_L 0x0607 +#define UCA1BR1_H 0x0608 +#define UCA1MCTL_ 0x0608 +#define UCA1MCTL_L 0x0608 +#define UCA1MCTL_H 0x0609 +#define UCA1STAT_ 0x060A +#define UCA1STAT_L 0x060A +#define UCA1STAT_H 0x060B +#define UCA1RXBUF 0x060C +#define UCA1RXBUF_L 0x060C +#define UCA1RXBUF_H 0x060D +#define UCA1TXBUF 0x060E +#define UCA1TXBUF_L 0x060E +#define UCA1TXBUF_H 0x060F +#define UCA1ABCTL 0x0610 +#define UCA1ABCTL_L 0x0610 +#define UCA1ABCTL_H 0x0611 +#define UCA1IRTCTL 0x0612 +#define UCA1IRTCTL_L 0x0612 +#define UCA1IRTCTL_H 0x0613 +#define UCA1IRRCTL 0x0613 +#define UCA1IRRCTL_L 0x0613 +#define UCA1IRRCTL_H 0x0614 +#define UCA1IE_ 0x061C +#define UCA1IE_L_ 0x061C +#define UCA1IE_H_ 0x061D +#define UCA1IFG_ 0x061D +#define UCA1IFG_L 0x061D +#define UCA1IFG_H 0x061E +#define UCA1IV_ 0x061E +#define UCA1IV_L_ 0x061E +#define UCA1IV_H_ 0x061F +#define UCB1CTL0_ 0x0621 +#define UCB1CTL0_L 0x0621 +#define UCB1CTL0_H 0x0622 +#define UCB1CTL1_ 0x0620 +#define UCB1CTL1_L 0x0620 +#define UCB1CTL1_H 0x0621 +#define UCB1BR0_ 0x0626 +#define UCB1BR0_L 0x0626 +#define UCB1BR0_H 0x0627 +#define UCB1BR1_ 0x0627 +#define UCB1BR1_L 0x0627 +#define UCB1BR1_H 0x0628 +#define UCB1STAT_ 0x062A +#define UCB1STAT_L 0x062A +#define UCB1STAT_H 0x062B +#define UCB1RXBUF 0x062C +#define UCB1RXBUF_L 0x062C +#define UCB1RXBUF_H 0x062D +#define UCB1TXBUF 0x062E +#define UCB1TXBUF_L 0x062E +#define UCB1TXBUF_H 0x062F +#define UCB1I2COA 0x0630 +#define UCB1I2COA_L 0x0630 +#define UCB1I2COA_H 0x0631 +#define UCB1I2CSA 0x0632 +#define UCB1I2CSA_L 0x0632 +#define UCB1I2CSA_H 0x0633 +#define UCB1IE_ 0x063C +#define UCB1IE_L_ 0x063C +#define UCB1IE_H_ 0x063D +#define UCB1IFG_ 0x063D +#define UCB1IFG_L 0x063D +#define UCB1IFG_H 0x063E +#define UCB1IV_ 0x063E +#define UCB1IV_L_ 0x063E +#define UCB1IV_H_ 0x063F +*/ +#endif /* __MSP430_HAS_USCI1_5__ */ + +#if defined(__MSP430_HAS_USCI2_5__) + +/* -------- USCI2_5 */ + +// tbd +/*#define UCA2CTL0_ 0x0641 +#define UCA2CTL0_L 0x0641 +#define UCA2CTL0_H 0x0642 +#define UCA2CTL1_ 0x0640 +#define UCA2CTL1_L 0x0640 +#define UCA2CTL1_H 0x0641 +#define UCA2BR0_ 0x0646 +#define UCA2BR0_L 0x0646 +#define UCA2BR0_H 0x0647 +#define UCA2BR1_ 0x0647 +#define UCA2BR1_L 0x0647 +#define UCA2BR1_H 0x0648 +#define UCA2MCTL_ 0x0648 +#define UCA2MCTL_L 0x0648 +#define UCA2MCTL_H 0x0649 +#define UCA2STAT_ 0x064A +#define UCA2STAT_L 0x064A +#define UCA2STAT_H 0x064B +#define UCA2RXBUF 0x064C +#define UCA2RXBUF_L 0x064C +#define UCA2RXBUF_H 0x064D +#define UCA2TXBUF 0x064E +#define UCA2TXBUF_L 0x064E +#define UCA2TXBUF_H 0x064F +#define UCA2ABCTL 0x0650 +#define UCA2ABCTL_L 0x0650 +#define UCA2ABCTL_H 0x0651 +#define UCA2IRTCTL 0x0652 +#define UCA2IRTCTL_L 0x0652 +#define UCA2IRTCTL_H 0x0653 +#define UCA2IRRCTL 0x0653 +#define UCA2IRRCTL_L 0x0653 +#define UCA2IRRCTL_H 0x0654 +#define UCA2IE_ 0x065C +#define UCA2IE_L_ 0x065C +#define UCA2IE_H_ 0x065D +#define UCA2IFG_ 0x065D +#define UCA2IFG_L 0x065D +#define UCA2IFG_H 0x065E +#define UCA2IV_ 0x065E +#define UCA2IV_L_ 0x065E +#define UCA2IV_H_ 0x065F +#define UCB2CTL0_ 0x0661 +#define UCB2CTL0_L 0x0661 +#define UCB2CTL0_H 0x0662 +#define UCB2CTL1_ 0x0660 +#define UCB2CTL1_L 0x0660 +#define UCB2CTL1_H 0x0661 +#define UCB2BR0_ 0x0666 +#define UCB2BR0_L 0x0666 +#define UCB2BR0_H 0x0667 +#define UCB2BR1_ 0x0667 +#define UCB2BR1_L 0x0667 +#define UCB2BR1_H 0x0668 +#define UCB2STAT_ 0x066A +#define UCB2STAT_L 0x066A +#define UCB2STAT_H 0x066B +#define UCB2RXBUF 0x066C +#define UCB2RXBUF_L 0x066C +#define UCB2RXBUF_H 0x066D +#define UCB2TXBUF 0x066E +#define UCB2TXBUF_L 0x066E +#define UCB2TXBUF_H 0x066F +#define UCB2I2COA 0x0670 +#define UCB2I2COA_L 0x0670 +#define UCB2I2COA_H 0x0671 +#define UCB2I2CSA 0x0672 +#define UCB2I2CSA_L 0x0672 +#define UCB2I2CSA_H 0x0673 +#define UCB2IE_ 0x067C +#define UCB2IE_L_ 0x067C +#define UCB2IE_H_ 0x067D +#define UCB2IFG_ 0x067D +#define UCB2IFG_L 0x067D +#define UCB2IFG_H 0x067E +#define UCB2IV_ 0x067E +#define UCB2IV_L_ 0x067E +#define UCB2IV_H_ 0x067F +*/ +#endif /* __MSP430_HAS_USCI2_5__ */ + +#if defined(__MSP430_HAS_USCI3_5__) + +/* -------- USCI3_5 */ +// tbd +/*#define UCA3CTL0_ 0x0681 +#define UCA3CTL0_L 0x0681 +#define UCA3CTL0_H 0x0682 +#define UCA3CTL1_ 0x0680 +#define UCA3CTL1_L 0x0680 +#define UCA3CTL1_H 0x0681 +#define UCA3BR0_ 0x0686 +#define UCA3BR0_L 0x0686 +#define UCA3BR0_H 0x0687 +#define UCA3BR1_ 0x0687 +#define UCA3BR1_L 0x0687 +#define UCA3BR1_H 0x0688 +#define UCA3MCTL_ 0x0688 +#define UCA3MCTL_L 0x0688 +#define UCA3MCTL_H 0x0689 +#define UCA3STAT_ 0x068A +#define UCA3STAT_L 0x068A +#define UCA3STAT_H 0x068B +#define UCA3RXBUF 0x068C +#define UCA3RXBUF_L 0x068C +#define UCA3RXBUF_H 0x068D +#define UCA3TXBUF 0x068E +#define UCA3TXBUF_L 0x068E +#define UCA3TXBUF_H 0x068F +#define UCA3ABCTL 0x0690 +#define UCA3ABCTL_L 0x0690 +#define UCA3ABCTL_H 0x0691 +#define UCA3IRTCTL 0x0692 +#define UCA3IRTCTL_L 0x0692 +#define UCA3IRTCTL_H 0x0693 +#define UCA3IRRCTL 0x0693 +#define UCA3IRRCTL_L 0x0693 +#define UCA3IRRCTL_H 0x0694 +#define UCA3IE_ 0x069C +#define UCA3IE_L_ 0x069C +#define UCA3IE_H_ 0x069D +#define UCA3IFG_ 0x069D +#define UCA3IFG_L 0x069D +#define UCA3IFG_H 0x069E +#define UCA3IV_ 0x069E +#define UCA3IV_L_ 0x069E +#define UCA3IV_H_ 0x069F +#define UCB3CTL0_ 0x06A1 +#define UCB3CTL0_L 0x06A1 +#define UCB3CTL0_H 0x06A2 +#define UCB3CTL1_ 0x06A0 +#define UCB3CTL1_L 0x06A0 +#define UCB3CTL1_H 0x06A1 +#define UCB3BR0_ 0x06A6 +#define UCB3BR0_L 0x06A6 +#define UCB3BR0_H 0x06A7 +#define UCB3BR1_ 0x06A7 +#define UCB3BR1_L 0x06A7 +#define UCB3BR1_H 0x06A8 +#define UCB3STAT_ 0x06AA +#define UCB3STAT_L 0x06AA +#define UCB3STAT_H 0x06AB +#define UCB3RXBUF 0x06AC +#define UCB3RXBUF_L 0x06AC +#define UCB3RXBUF_H 0x06AD +#define UCB3TXBUF 0x06AE +#define UCB3TXBUF_L 0x06AE +#define UCB3TXBUF_H 0x06AF +#define UCB3I2COA 0x06B0 +#define UCB3I2COA_L 0x06B0 +#define UCB3I2COA_H 0x06B1 +#define UCB3I2CSA 0x06B2 +#define UCB3I2CSA_L 0x06B2 +#define UCB3I2CSA_H 0x06B3 +#define UCB3IE_ 0x06BC +#define UCB3IE_L_ 0x06BC +#define UCB3IE_H_ 0x06BD +#define UCB3IFG_ 0x06BD +#define UCB3IFG_L 0x06BD +#define UCB3IFG_H 0x06BE +#define UCB3IV_ 0x06BE +#define UCB3IV_L_ 0x06BE +#define UCB3IV_H_ 0x06BF +*/ +#endif /* __MSP430_HAS_USCI3_5__ */ + #endif ------------------------------------------------------------------------------ OpenSolaris 2009.06 is a cutting edge operating system for enterprises looking to deploy the next generation of Solaris that includes the latest innovations from Sun and the OpenSource community. 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