Re: [RFC PATCH] LoongArch: Fix intermittent nptl/tst-cancel32 failure

On Wed, 2026-08-05 at 11:47 +0800, mengqinggang wrote:
>=20
> =E5=9C=A8 2026/8/5 11:33, Xi Ruoyao =E5=86=99=E9=81=93:
> > On Wed, 2026-08-05 at 10:09 +0800, mengqinggang wrote:
> > > =C2=A0=20
> > > Hi Wilco,
> > > =C2=A0=20
> > > I'm sorry, I don't think I fully understood your point.
> > > =C2=A0=C2=A0On LoongArch64:
> > > =C2=A0=C2=A0PTR_DEMANGLE2 (sp, t0, t1)
> > > expand to:
> > >=20
> > > rotri.d=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 $sp, $t0, 0x1=
1
> > > xor=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 $sp, $sp, $t1
> > > =C2=A0=20
> > > =C2=A0=C2=A0The SP register is partially updated between the rotri.d =
and xor
> > > instructions.
> > > =C2=A0=C2=A0Using this value in the pthread_cancel path may cause a S=
IGSEGV.
> > > I think this issue is not relate to t0 register.
> > Meaning we can simply expand it to
> >=20
> > rotri.d $t0, $t0, 0x11
> > xor=C2=A0=C2=A0=C2=A0=C2=A0 $sp, $sp, $t1
>=20
> Perhaps it should be:
> rotri.d $t0, $t0, 0x11
> xor=C2=A0=C2=A0=C2=A0=C2=A0 $sp, $t0, $t1

Yes.
>=20
> > instead of introducing t2.=C2=A0 (With a comment for PTR_DEMANGLE2 sayi=
ng
> > it
> > will clobber the input in t0.)
> >=20

--=20
Xi Ruoyao <[email protected]>