riscv: configure.ac bug fix for misaligned access when __riscv_misaligned_slow
Gedare Bloom <[email protected]> Thu, 30 Apr 2026 23:28:59 -0600
| Newsgroups | gmane.comp.lib.newlib |
|---|---|
| Message-ID | <CAC82fA0bEoVPA3mSGT5WpupseOa9odE2N-EeuBtmL5ii_ejt4A@mail.gmail.com> |
memcmp is generating data alignment errors on risc-v targets where the
hw does not allow unaligned access. This behavior was observed on
microchip polarfire with rtems. Here is the code generated:
000000008000bb34 <memcmp>:
8000bb34: 469d li a3,7
8000bb36: 00c6fb63 bgeu a3,a2,8000bb4c <memcmp+0x18>
8000bb3a: 6118 ld a4,0(a0)
8000bb3c: 619c ld a5,0(a1)
You can see that 8000bb3a will cause a fault if a0 is not aligned and
hw does not support it.
riscv-rtems7-gcc -dM -E - < /dev/null | grep aligned
#define __riscv_misaligned_slow 1
Attached fix corrects this. Generated code is now:
00000008000baf6 <memcmp>:
8000baf6: 469d li a3,7
8000baf8: 04c6f063 bgeu a3,a2,8000bb38 <memcmp+0x42>
8000bafc: 00a5e7b3 or a5,a1,a0
8000bb00: 8b9d andi a5,a5,7
8000bb02: c395 beqz a5,8000bb26 <memcmp+0x30>
8000bb04: 167d addi a2,a2,-1
8000bb06: 0605 addi a2,a2,1
8000bb08: 962a add a2,a2,a0
8000bb0a: a019 j 8000bb10 <memcmp+0x1a>
Now we have the check at 8000bb02 that will handle alignment and
falls-thru to byte-by-byte copy, or jumps to aligned long copies.
Gedare
0001-riscv-avoid-misaligned-accesses-if-__riscv_misaligne.patch
(text/x-patch, 1 KB)
From 74564292ffd4c0f2baa4d99715cce614dd4572f6 Mon Sep 17 00:00:00 2001 From: Gedare Bloom <[email protected]> Date: Thu, 30 Apr 2026 11:10:53 -0600 Subject: [PATCH] riscv: avoid misaligned accesses if __riscv_misaligned_slow The configure rule for misaligned accesses is too wide by including __riscv_misaligned_fast or __riscv_misaligned_slow for enabling the HW supported misaligned access. --- newlib/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/newlib/configure.ac b/newlib/configure.ac index a4807830e..4640e69c5 100644 --- a/newlib/configure.ac +++ b/newlib/configure.ac @@ -555,7 +555,7 @@ if test "x${newlib_hw_misaligned_access}" = "x"; then AC_CACHE_CHECK([if $CC has enabled misaligned hardware access], [newlib_cv_hw_misaligned_access], [dnl cat > conftest.c <<EOF -#if __riscv_misaligned_fast || __riscv_misaligned_slow +#if __riscv_misaligned_fast void misalign_access_supported(void) {} #else #error "misaligned access is not supported" -- 2.47.3