Re: fiasco.oc i.MX7d port

Hi Marc,

On Mon Oct 10, 2016 at 10:46:46 +0200, Marc CHALAND wrote:
> Le samedi 8 octobre 2016, Adam Lackorzynski <[email protected]
> <javascript:_e(%7B%7D,'cvml','[email protected]');>> a écrit :
> 
> > Hi,
> >
> > On Wed Oct 05, 2016 at 19:50:45 +0200, Marc CHALAND wrote:
> >
> > > So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?
> >
> > You mean CPU1? Did you also add different setting for SCR? It seems to
> > be different for imx7.
> >
> 
> Yes, I mean CPU1. I created a file platform_control-arm-imx7.cpp which sets
> power up on CPU1 through GPC registers, sets tramp addr into SRC registers
> and enables CORE1 like linux does.  See attachment.

I do not see anything obviously wrong right away. I assume it passes the
while loop?



Adam
-- 
Adam                 [email protected]
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/