Re: I/O flexpages / new mapping DB issue with overlapping ports

[Frank Mehnert]
> On Thursday 08 June 2006 20:06, Espen Skoglund wrote:
>> [Frank Mehnert]
>>> Another related question comes up: Since the kernel allows Sigma0
>>> to map every I/O flexpage the responsibility lies at the
>>> privileged tasks to prevent mapping of I/O ports the kernel uses
>>> itself. I assume the same applies to MSRs. However, neither Sigma0
>>> nor root task have any information about the I/O ports and MSRs
>>> the kernel is using.
>> 
>> [...]
>> 
>> There was at some stage some loose talk about implementing an MSR
>> space with similar semantics as the IO space.  This is quite
>> trivial to do using the current code base in Pistachio.  Whether
>> there are any real benefits to doing so is a different question.

> In difference to the IO space the MSR space would contain only one
> fpage covering the whole MSR space as long as we don't talk about
> VT. Since I'm not aware of any MSR which is frequently read or
> written, there is probably no reason to allow non-privileged tasks
> the access to MSRs.

Yeah.  The best examples I can think of are the MSRs for debugging and
performance monitoring.  Anyhow, there's nothing stopping you from
mapping single MSRs if you want to.  The code base for doing so is
there.

	eSk