PG needs to be enabled before PGE

Hi,

I just thought I give you a heads-up: When looking at the Intel
manuals I found the following in Vol 3 Section 2 (Control registers,
around page 2-17):

"paging must be enabled [...] before the PGE flag is set"

There is no rationale why this is the case.  It just says that
reversing the sequence may impact correctness and performance.

The concern is probably that stale TLB entries may not be flushed, so
there should be a window where the global flag is cleared and the TLB
flushed completely.  But I can not be sure.  Maybe you know better
than the Intel manual (if you know, please let me know as well!).

In L4 Pistachio, src/glue/v4-ia32/init.cc, the sequence is reversed.

Thanks,
Marcus