TCR and Stack in the PowerPC implementation

Maybe someone (Joshua) could bring some light into the stack issue on
PowerPC. I tried to understand the code, but there are still a lot of
things hiding in darkness. :-(

1.) In Appendix C you are using negative offsets for the TCR fields.
Why? The stack pointer (r1) should point to the lowest address and thus
only positive offsets should be valid. And sometimes you also use
negative offsets in inlined assembler (like in tcb_t::switch_to()). That
confuses me. :-(

2.) Where is the machine state saved on a thread switch? Is the threads
stack used?

3.) How many stacks are there? The kernel stack per thread is located in
the KTCB area following the TCB entry, isn't it? And the thread has it's
own user level stack, I assume? And there must be a stack for kernel
internal function calls?

4.) Where would I find the saved machine state of a runnable thread?

I hope someone (Jushua) finds time to answer these questions. ;-)

Best,

Martin.