DMA related cache coherency issues

Hi there,

I have an OHCI (Firewire) controller that reads and stores data from  
and to
local physical (memory) addresses on behalf of a remote host. That works
very well within the firmware environment but breaks once L4 is loaded.
If I try to access said memory addresses from within the kernel (kdb)  
the
OHCI controller sees instantly any changes made to the memory by the CPU
but the other way around the CPU doesn't see any changes made by the  
OHCI
and always fetches invalid values. So I suppose reads from memory are  
cached
and somehow don't get invalidated once changes are made. I tried to  
force
the invalidation of the cache prior to every read, but that didn't work.

So basically what I want is this:

- Chose a physical memory page designated to exchange data between  
CPU and OHCI.
- Map said page to kernel and user address spaces (without caching).

The purpose is to get some basic debug I/O on systems that lack any
kind legacy ports (serial/vga/i8042...) like EFI/x86 based Macs.

Any ideas?

Thank you!

- Sebastian Gregorzyk