Re: Constant assignments in co-simulation

On 5/26/2015 10:57 AM, Nikolay Kavaldjiev wrote:
> Thanks Chris!
>
> I don't think that preserving the combinatorial assignment is my issue,
> because the module I have:
<snip>
>
> assign b = 1;
> assign aBit = b;
> assign aByte = 85;
>
>
> Which to me looks OK.

I agree, the conversion look fine.

>
> My problem comes when I do co-simulation with Icarus. Then instead of
> observing the expected aBit==True and aByte==0x55, I observe aBit==False
> and aByte==0, which are the default values of the MyHDL signals connected
> co-simulated module.
>

Ahhh yes, you are trying to Cosimulate a design
that has no inputs.  I forget the particular
reasons but I don't believe it is possible to
Cosimulate such a limited design.
http://docs.myhdl.org/en/latest/manual/cosimulation.html#restrictions

See the example in the documents for a basic
example:
http://docs.myhdl.org/en/latest/manual/cosimulation.html#co-simulation-with-verilog

You shouldn't have any issue Cosimulating a
complete design.

Regards,
Chris





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