Re: Constant assignments in co-simulation

> Ahhh yes, you are trying to Cosimulate a design
> that has no inputs.  I forget the particular
> reasons but I don't believe it is possible to
> Cosimulate such a limited design.
> http://docs.myhdl.org/en/latest/manual/cosimulation.html#restrictions

To exclude this as a possibility I modified the example module in the gist (
https://gist.github.com/nkavaldj/7cc69372246e64d68f58) to have an input and
I still have the same issue with co-simulation (only with co-simulation).

The modified code:

def const_assign(x, y, aBit, aByte):

    @always_comb
    def logic():
        y.next = x + 5
        aBit.next = True
        aByte.next = 55

    return logic


Converted code:

module const_assign (
    x,
    y,
    aBit,
    aByte
);

input [7:0] x;
output [7:0] y;
wire [7:0] y;
output aBit;
wire aBit;
output [7:0] aByte;
wire [7:0] aByte;

assign y = (x + 5);
assign aBit = 1'b1;
assign aByte = 55;

endmodule



> You shouldn't have any issue Cosimulating a
> complete design.

Actually we have the issue in a large/complete design with plenty of inputs
and outputs. The gist is just a minimalistic example that demonstrates the
issue. We are using myhdl for more that two years now, including
co-simulation, so it should not be a beginners issue. I hit the issue a
week ago, and I cannot move since.


Regards,

Nikolay


On 26 May 2015 at 18:25, Christopher Felton <[email protected]> wrote:

> On 5/26/2015 10:57 AM, Nikolay Kavaldjiev wrote:
> > Thanks Chris!
> >
> > I don't think that preserving the combinatorial assignment is my issue,
> > because the module I have:
> <snip>
> >
> > assign b = 1;
> > assign aBit = b;
> > assign aByte = 85;
> >
> >
> > Which to me looks OK.
>
> I agree, the conversion look fine.
>
> >
> > My problem comes when I do co-simulation with Icarus. Then instead of
> > observing the expected aBit==True and aByte==0x55, I observe aBit==False
> > and aByte==0, which are the default values of the MyHDL signals connected
> > co-simulated module.
> >
>
> Ahhh yes, you are trying to Cosimulate a design
> that has no inputs.  I forget the particular
> reasons but I don't believe it is possible to
> Cosimulate such a limited design.
> http://docs.myhdl.org/en/latest/manual/cosimulation.html#restrictions
>
> See the example in the documents for a basic
> example:
>
> http://docs.myhdl.org/en/latest/manual/cosimulation.html#co-simulation-with-verilog
>
> You shouldn't have any issue Cosimulating a
> complete design.
>
> Regards,
> Chris
>
>
>
>
>
>
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