Re: Constant assignments in co-simulation

On 5 June 2015 at 13:29, Henry Gomersall <[email protected]> wrote:

> I would have expected the Verilog to work as expected. Does it need a
bitwidth or something?

I would also expect so. My guess is that the problem is in the interface
between MyHDL and Icarus. The OutPort never changes value, the expression
assign OutPort = CONSTANT is never evaluated, the value on the MyHDL side
is never updated... something like that. When you put the assignment in a
alway @ section which is evaluated, the value on the MyHDL side in correct.


> What do other simulators do?

I haven't tried with other simulators.

Nkolay



On 5 June 2015 at 13:29, Henry Gomersall <[email protected]> wrote:

>  On 05/06/15 12:19, Nikolay Kavaldjiev wrote:
>
> During co-simulation we expect to see the output ports aBit and aByte of
> the co-simulated module to be assigned values True and 55 respectively.
> However, the values that we actually see are different, False and 0. These
> are the default values of the signals my_bit and my_byte connected to the
> co-simulated module.
>
> The Reason
>
> We are not sure what the reason for this problem is, but what causes the
> problem seams to be a Verilog continuous assignments of type:
>
> assign OutPort = CONSTANT
>
>
> I would have expected the Verilog to work as expected. Does it need a
> bitwidth or something?
>
> What do other simulators do?
>
> Henry
>
>
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