tri1 and tri0 net types

Hi,

I am starting to experiment with MyHDL and I noticed that there is a feature 
missing, namely an equivalent to tri1 and tri0 net types in Verilog. They are 
used to model a net with a pull-up or pull-down resistor, e.g. an I2C bus.

I believe that this feature could add to completeness of the language, and 
also that it is quite trivial to implement it. The user would specify a 
default value to TristateSignal constructor and the resolve function will 
honor the default value instead of just returning None when no driver is 
driving the net.

What do the others think?

Best Regards,
(the other) Jan


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