Re: tri1 and tri0 net types

On 6/9/2015 4:32 PM, Jan Marjanovic wrote:
> Hi,
>
> I am starting to experiment with MyHDL and I noticed that there is a feature
> missing, namely an equivalent to tri1 and tri0 net types in Verilog. They are
> used to model a net with a pull-up or pull-down resistor, e.g. an I2C bus.

You should be able to do what you want with the
TristateSignal [1].

There were some questions recently on IRC, couple
examples from that discussion:

https://gist.github.com/cfelton/748f5364a1a483f1e982
https://gist.github.com/josyb/c816d585e12ae397627b
https://gist.github.com/cfelton/6119313

There is an outstanding TristateSignal conversion
bug but with any luck (resources) we should have
it fixed soon ...

Hope that helps,
Chris

[1] 
http://docs.myhdl.org/en/latest/manual/reference.html?highlight=tracesignals#myhdl.traceSignals




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