Re: Interfaces in hierarchcal way

Josy Boelen <[email protected]>
Newsgroups gmane.comp.python.myhdl
Message-ID <[email protected]>
Christopher Felton <chris.felton <at> gmail.com> writes:


> I don't know, I really dislike Qsys and the whole
> approach.  It is impossible to create flexible and
> modular systems.
> 
> And yes you might be missing something (or I am :).
> I think in this case an AXI subsystem was created
> in myhdl and is being converted to Verilog and
> integrated with more Verilog presumably (?).
> 
> Regards,
> Chris
> 

We already talked about that, and yes you can't create parametrizable 
systems with Qsys.
But I'm not sure that bespoke AXI subsystems are that flexible either. 
And connecting them all up in an hierarchical way can be tedious. I have 
only used Avalon MM interfaces and am quite OK with wiring them in Qsys, 
but then our Qsys projects are very 'fixed'. 
I have been contemplating on abandoning Qsys, but then I need a good 
alternative for connecting those master and slave interfaces together.

I have been working on a Xilinx project (consulting for) and was 
impressed by the overhead of building such an AXI system manually.

Now I was just curious, and I had hoped that Jos Huysken enlightened me 
:)


Regards,

Josy


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