Re: Interfaces in hierarchcal way

Hi guys,

> 
> We already talked about that, and yes you can't create parametrizable 
> systems with Qsys.
> ...
> I have been contemplating on abandoning Qsys, but then I need a good 
> alternative for connecting those master and slave interfaces together.
> 

Having a deja vu here...
I've found all the SOPC/Qsys and their Xilinx/Lattice counterparts not
really friendly for maintenance, so I've ended up with an approach based
on GNU make, kconfig (linux kernel config) and an XML device description
(called DClib/devdesc). Like IP-XACT, but way less complex. Could be
enhanced to spit out MyHDL (currently, it can only generate VHDL based
Wishbone-capable SoCs). There's also a graphical tool called "kactus2",
but I haven't looked at it in detail.
The XML approach turned out to be quite robust and future compatible,
unlike the known migration nightmares that make you freeze old software
versions in a VM...

Once hierarchy can be maintained in MyHDL, this might become very
interesting, due to a vast amount of powerful XML processing tools in
the Python domain.

Greetings,

- Martin

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