Re: Interfaces in hierarchcal way

Jos Huisken <[email protected]>
Newsgroups gmane.comp.python.myhdl
Message-ID <[email protected]>
Josy Boelen <josyboelen <at> gmail.com> writes:

> We already talked about that, and yes you can't create parametrizable 
> systems with Qsys.
> But I'm not sure that bespoke AXI subsystems are that flexible either. 
> And connecting them all up in an hierarchical way can be tedious. I have 
> only used Avalon MM interfaces and am quite OK with wiring them in Qsys, 
> but then our Qsys projects are very 'fixed'. 

The idea is to use the lightweight AXI master for configuring both the 
streaming interfaces and the connected IP, and that the axi-master and 
axi-slave only serve as stream drivers and stream receivers respectively.
So configuration can be quite simple, I guess. But streaming interfaces 
are blocking so deadlock may occur: but that problem should be avoided by 
higher level mapping techniques.
This looks like a nice simple model to me, which can later be used easily 
toward silicon implementation. I prefer platform independence as much as 
reasonably possible, and think that this would also work out for Xilinx  
(although I haven't checked it yet)

Regards,
Jos



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