Re: Interfaces in hierarchcal way

Using MyHDL, I did create a full DMA controller for transferring radio
data from our digital receivers to user applications.  The controller
accepts data from our DDC's via AXI4-Stream signaling, and then it sends
the PCIe MWr TLP's (packets) to the Xilinx PCIe interface over
AXI4-Stream as well.  The Linux driver supports zero-copy I/O for direct
transfer into user application buffers, and MSI-X with message
ring-buffers for relaying status back to the driver.  There are no
kernel "bounce" buffers and thus no time wasted on memcpy.  This way,
customers may happily buy and plug more of our hardware into their
hosts, or they may use their hosts' available CPU and memory bandwidth
for more intensive signal processing.

I briefly looked at XillyBus, but opted to design my own low-latency scheme.

Leading up to and in support of this DMA controller, I did create a few
smaller AXI4-Stream building blocks in MyHDL such as synchronous FIFO's,
skid-buffers, and priority arbiters.  (yes, even though Xilinx offers
equivalent blocks...)  They were written around the time of MyHDL 0.7
and 0.8-dev (before MyHDL's hierarchical signal ), so I did end-up
implementing a number of work-arounds to avoid some MyHDL peculiarities
at the time.  In summary, these smaller [1] vendor-agnostic streaming
blocks would work just fine on Altera, but their code is pretty ugly
with the work-arounds.  Perhaps with MyHDL 0.9, a rewrite of these
blocks would make them less internally ugly and thus worthy of being shared.

Footnote:
1] For my larger DMA controller block, its PCIe output AXI4-S interface
is written to expect the signaling that the Xilinx IP core uses over the
"user" bits, so I'm not sure how cleanly this particular block would
port from Xilinx to Altera.


On 7/13/15 2:23 AM, Jos Huisken wrote:
> Josy Boelen <josyboelen <at> gmail.com> writes:
>
>> Jos Huisken <jos.huisken <at> gmail.com> writes:
>>
>>> I was trying to create an AXI subsystem for Altera Cyclone V 
> boards... 
>> Excuse me for barging in, but if you are using Altera components, 
> wouldn't 
>> it be easier to use Qsys to connect all those AXI (and other) 
> components? 
>> Or am I missing something?
>>
>> Regards,
>>
>> Josy
> Hi all,
>
> The idea is ultimately to create mainly streaming interfaces toward 
> hardware, i.e. AXI4S, the amount of streaming interfaces parameterized 
> and usable from a device driver in linux.
> You can maybe imagine that it becomes conveniently feasible to use 
> hardware accelerators and, for instance, use them from GNU-Radio.
> I haven't found that much, except maybe 'xillybus' which seems like a 
> solution.
> I'm using Qsys as well, but indeed as Chris mentioned, not easily 
> parameterized and missing the IP to go streaming.
>
> Maybe others have been looking into such architectural setup, I expect 
> at least that I'm not unique in realizing something like this.
>
> Regards,
> Jos
>
>
>
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