Re: simulation appears okay when programmed not getting all signals.

Hi All,
Most of the files in the pc_fast_blinker_jpeg folder have 2 options --test to run a simulation 

and --convert to create a Verilog file.  Trying to follow Chris's examples.

The file test_top.py imports several files


from jpeg import dwt
from signed2twoscomplement import signed2twoscomplement
from l2r import lift2res
from sh_reg import ShiftReg, toSig
from para2ser import para2ser
from div_clk import div_4
from jpeg_sig import *

Running "python test_top.py --test" is my overall goal. 


Testing the transfer from the FPGA to RPi2B which uses para2ser.py.
is why I am working with "python test_send31.py --test".  On CAT-Board 
the clock is 100MHz which I believed was too fast for the RPi2B.  That
is why I divided by 4.  The signal clkInOut is 25MHz.  The signal ld_o
is when the 4 10 bit values get loaded in pp0 which is then shifted out
using signal ss0.  On the RPi I can see the signals clkInOut & ld_o
changing state but the signal ss0 is always 0.
 

To get a bit (Xula2-LX9) or bin (CAT-Board) file I use "python ex_xula_sending.py" 
with Xilinx Tools on a  Ubuntu system.  

On a RPi2B with Yosys, Arachne-pnr, IcePack "python ex_sending.py" 
creates the files to program the ICE40. The gpio_test.py is used to read the GPIO on the RPi2B. 


If I can provide any additional information just let me know.
Thanks,
Edward Vidal Jr. e-mail [email protected] 915-595-1613 

    On Saturday, January 23, 2016 1:21 AM, Jan Coombs <[email protected]> wrote:
 

 hi Edward, 

It was good to speak with you earlier this week.

On Sat, 23 Jan 2016 01:18:28 +0000 (UTC)
Edward Vidal <[email protected]> wrote:

> Hello All,   
>     ran python test_sending31.py --test which generates tb.vcd 

I cloned your git repo, installed rhea properly, changed to
the relevant folder:

/home/jan/.../EdwardVidal/git/jpeg-2000-test/pc_fast_blinker_jpeg

then ran the above command: "pythontest_sending31.py"  and found
only these new files:

./
├── [2016-01-23_07:40:11]  iceriver
│   ├── [2016-01-23_07:40:11]  build_iceriver.log
│   ├── [2016-01-23_07:40:11]  catboard.bin
│   ├── [2016-01-23_07:40:09]  catboard.blif
│   ├── [2016-01-23_07:40:08]  catboard.pcf
│   ├── [2016-01-23_07:40:11]  catboard.txt
│   ├── [2016-01-23_07:40:06]  catboard.v
│   ├── [2016-01-23_07:40:08]  catboard.ys
│   └── [2016-01-23_06:39:58]  pck_myhdl_10.vhd
├── [2016-01-23_07:44:51]  test_sending31.py
2 directories, 51 files


The related .vcd (signal trace) file you refer to seems to be
missing, what is needed to fix this? 


Jan Coombs

------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140

_______________________________________________
myhdl-list mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/myhdl-list