Re: A module that connects signals if names match

On 2/24/2016 10:00 PM, Ben Reynwar wrote:
> And five minutes after posting I found a bug in my code that
> explained why the simulation wasn't working.  I had inputs and
> outputs wrong way round! However, I still am having issues with the
> verilog generation.


It looks like it is working, what is the issue you are
having?

There is a known side-effect when converting top-level
interface ports.  When converting the interfaces some
name-mangling occurs, the Python compiler does this
renaming.

Regards,
Chris


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