Re: A module that connects signals if names match

Thanks for the help Chris.  I've updated the code so that I have 3 input
signals (i_a, i_b, i_c) and 2 output signals (o_b, o_c).

The name mangling converts both i_b and i_c to i, and both o_b and o_c to
o.  How should I get around this issue?

On Thu, Feb 25, 2016 at 6:49 AM, Christopher Felton <[email protected]>
wrote:

> On 2/24/2016 10:00 PM, Ben Reynwar wrote:
> > And five minutes after posting I found a bug in my code that
> > explained why the simulation wasn't working.  I had inputs and
> > outputs wrong way round! However, I still am having issues with the
> > verilog generation.
>
>
> It looks like it is working, what is the issue you are
> having?
>
> There is a known side-effect when converting top-level
> interface ports.  When converting the interfaces some
> name-mangling occurs, the Python compiler does this
> renaming.
>
> Regards,
> Chris
>
>
>
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