Re: Thanks for MyHDL & PLL's

>>
>> if that isn't possible, could someone give me an example wrapped in a
>> custom verilog clause?
>
> This isn't a minimilistic example or an iCE PLL example
> but it is an example of wrapping a Xilinx MMCM
> https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py
>

Here is an example wrapping an iCE40 (?) `SB_IO`:
https://github.com/xesscorp/CAT-Board/blob/master/tests/ice40_primitives.py

Regards,
Chris



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