Re: Thanks for MyHDL & PLL's

 >This isn't a minimilistic example or an iCE PLL example but it is an 
example of wrapping a Xilinx >MMCM 
https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py 
 >Regards, Chris

lol - yeah ya not kidding it's going to take me this side of next month 
just to figure out how to get that working!!!

Don't suppose you've got a saner example of including a verilog module 
within a MyHDL do you? it's either way less complex than it looks or I'm 
missing something here!

thx
Chris


------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140