Re: Thanks for MyHDL & PLL's

On Thu, 25 Feb 2016 21:03:22 +0000
Mr C Camacho <[email protected]> wrote:

> Don't suppose you've got a saner example of including a
> verilog module within a MyHDL do you? it's either way less
> complex than it looks or I'm missing something here!

I have wrapped Lattice library components to make them simulate
or export for synthesis.

The smallest wrapper I have is for a Lattice XO2 internal osc
- 47 lines. 

Have also an iCE40 SB_RAM256X16.py with initialization, which I
have used. 

I also started wrapping everything from the iCE40 primitive
library, thinking I might ignore the synthesis tool and do it all
in MyHDL, but most of this is untested. 

Have you noticed that the icestorm tools can program an iCE40
part in just 2s?

Let me know if you'd like anything emailed. 

Jan Coombs. 
-- 
email valid at present...

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